Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.

Abstract: Techniques are provided for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. A reduced state sequence estimation (RSSE) decoder is provided for a multidimensional code. A multidimensional code symbol comprises a number of symbol components of lower dimensionality. The RSSE decodes comprises at least one branch metric unit that calculates branch metrics for a received signal based on intersymbol interference and intrasymbol interference estimates, the at least one branch metric unit compensating for intrasymbol interference caused by symbol components within a current multidimensional code symbol; and a decision feedback unit that processes survivor symbols to calculate the intersymbol interference estimates for different code states of the multidimensional code and channels used to transmit the multidimensional code.

Abstract: A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.

Abstract: An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer.

Abstract: The present invention provides an HDD performance enhancement system that utilizes excess disk capacity as cache memory to enhance the I/O performance of the drive. The cache memory is distributed throughout the disk, for example in alternating tracks, sectors dedicated to serving as cache, or other distributed cache track segments or segment groups. Distributing the cache throughout the disk reduces the physical distance of the I/O head to the closest available cache location. The system minimizes the write seek time by storing write data in the closest available cache location. High utilization data blocks are stored in multiple cache location locations to reduce read seek time for high utilization data. The cached data is eventually written to permanent memory and cleared from the cache during idle or low data storage utilization periods.

Abstract: Described embodiments provide a system having at least two network processors that each have a plurality of processing modules. The processing modules process a packet in a task pipeline by transmitting task messages to other processing modules on a task ring, the task messages related to desired processing of the packet. A series of tasks within a network processor may result in no processing or reduced processing for certain processing modules creating a virtual pipeline depending on the packet received by the network processor. At least two of the network processors communicate tasks. This communication allows ter the extension of the virtual pipeline of or IC network processor to at least two network processors.

Abstract: A method of enhancing read performance in array-reader hardware includes generating, by the array-reader hardware, a plurality of signals, according to data read from a magnetic disk, and canceling at least a portion of cross-talk in the plurality of signals to generate a plurality of corrected signals.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including utilization of different scaling values on a portion by portion basis during the data decoding.

Abstract: Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for mis-correction detection and correction in a data processing system.

Abstract: A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded.

Abstract: An image processing system comprises an image processor implemented using at least one processing device and adapted for coupling to an image source, such as a depth imager. The image processor is configured to compute a convergence matrix and a noise threshold matrix, to estimate background information of an image utilizing the convergence matrix, and to eliminate at least a portion of the background information from the image utilizing the noise threshold matrix. The background estimation and elimination may involve the generation of static and dynamic background masks that include elements indicating which pixels of the image are part of respective static and dynamic background information. The computing, estimating and eliminating operations may be performed over a sequence of depth images, such as frames of a 3D video signal, with the convergence and noise threshold matrices being recomputed for each of at least a subset of the depth images.

Abstract: Systems and methods herein provide for managing devices through a Serial Attached Small Computer System Interface (SAS) expander. The SAS expander includes a processor adapted to detect deadlock conditions in a SAS environment. In one embodiment, the SAS expander is operable to detect an Open Address Frame associated with a connection request from a source device to a destination device. The Open Address Frame includes a source address and a destination address associated with the source device and the destination device, respectively. The expander receives an arbitration in progress status on a partial pathway that is associated with the connection request. The expander is further operable to modify the Open Address Frame to include a deadlock indicator and forward the modified Open Address Frame on the partial pathway. When the modified Open Address Frame is received, the expander initiates pathway recovery upon determination that the deadlock indicator is valid.

Abstract: A switch includes registers, a parser and port selection logic. The registers store an address in multiple locations. The address defines a bridge domain. Each bridge domain defines a set of switch ports. The parser identifies when a received frame includes a virtual local area network (VLAN) identifier. The parser uses the VLAN identifier to locate the address in the registers. The port selection logic is responsive to one of a first index from a first table that includes port identifiers and the bridge domain and a second index from a second table that includes VLAN identifiers. The switch is configured by defining an address scheme, inserting an address field in the first and second tables, and generating maps from the tables. The maps direct the port selection logic to direct received frames to desired port(s).

Abstract: An aspect of present invention is to provide a temperature control system for a solar cell module, capable of controlling a solar cell module to maintain a proper temperature, the temperature control system comprises: a temperature sensor configured to measure a temperature of the solar cell module; a fluid tube having therein a path along which a temperature controlling fluid flows; a pump configured to supply a temperature controlling fluid which flows along the fluid tube; and an inverter configured to drive the pump such that the temperature controlling fluid is supplied, if the current temperature of m the solar cell module is not lower than the pre-stored first pump driving reference temperature, or if the current temperature of the solar cell module is not higher than the pre-stored second pump driving reference temperature.

Abstract: A magnetic recording system includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a modulator operable to combine the analog signals to yield a frequency division multiplexed signal, a demodulator operable to yield a plurality of demodulated signals from the frequency division multiplexed signal corresponding to each channel of the array, and a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.

Abstract: An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a user area and a non-user area. The user area is generally enabled to store and retrieve data in a logical block address space of a host. The non-user area stores a failure-specific recovery routine. The controller may be communicatively coupled to the non-volatile memory. The controller is generally enabled, when operationally coupled to the host, (i) to respond to host commands to read and to write data into the user area of the non-volatile memory and (ii) upon detection of a predefined failure of a controller boot process, to respond to host read requests by returning the failure-specific recovery routine stored in the non-user area of the non-volatile memory.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit is configured to generate an access request having a first address. The second circuit is configured to (i) initiate a change in a load value of a cache system in response to the access request. The cache system has a plurality of levels. The load value represents a work load on the cache system. The second circuit is further configured to (ii) generate a second address from the first address in response to the load value and (iii) route the access request to one of the levels in the cache system in response to the second address.

Abstract: Disclosed is a storage device interface. The storage device interface includes a plurality of PCIe device request engines. These PCIe device request engines receive I/O commands formatted for a respective one of a plurality of PCIe storage device communication standards. The storage device interface also includes a plurality of PCIe device completion engines. These PCIe device completion engines receive notifications of command completions from a plurality of PCIe storage devices that communicate using the aforementioned plurality of PCIe storage device communication standards. These notifications are validated. If an error is detected, processing of notifications of command completions associated with that device are blocked until the error is resolved. The plurality of PCIe device request engines and the PCIe device completion engines operate concurrently to process received I/O commands and received command completions.