Abstract: Various embodiments of the present invention provide systems and methods for media defect detection.

Abstract: Systems and methods relating generally to sensing information, and more particularly to systems and methods for utilizing multiple readers to sense information.

Abstract: A modified or host driver operable on a host computer communicates with a host interface of a PCIe adapter. A controller memory space is managed by the kernel space of the host operating system. The modified driver entirely avoids the overhead associated with making a copy from the application or user space to a separate kernel space managed by the operating system in the host computer. The modified driver uses a base address register to identify the location of the cache storage in the controller memory space. The size of the cache store is communicated to the modified driver upon a power on initialization of the PCIe adapter and the host computer. A memory map managed by the modified driver identifies cache storage locations as an offset from the base address register.

Abstract: An apparatus includes a synchronization block and a physical coding sublayer block. The synchronization block may be configured to determine a position of a start of frame delimiter. The physical coding sublayer block may be configured to measure a delay through the physical coding sublayer block and provide delay and delay variation compensation based upon the measured delay.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit is configured to generate a first intermediate signal by expanding a first input signal subjected to a quantization. The second circuit is configured to generate a second intermediate signal based on a second input signal. The second intermediate signal approximates an echo in the first input signal caused by the second input signal. The second circuit is also configured to generate a third intermediate signal by companding the second intermediate signal to compensate the quantization of the first input signal.

Abstract: A first communication device calculates a data error detection code for detecting an error in data by using the data and a virtual sequence number, and generates a packet comprising the data and the data error detection code. The packet does not include the virtual sequence number which is used for calculating error detection. The first communication device transmits the packet to a second communication device.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.

Abstract: A data storage controller exposes information stored in a locally managed volatile memory store to a host system. The locally managed volatile memory store is mapped to a corresponding portion of a peripheral component interconnect express (PCIe) compliant memory space managed by the host system. Backup logic in the data storage controller responds to a power event detected at the interface between the data storage controller and the host system by copying the contents of the volatile memory store to a non-volatile memory store on the data storage controller. Restore logic restores a data storage controller state by copying the contents of the non-volatile memory store to the locally managed volatile memory store upon the application of power such that the data in the volatile memory store is persistent even in the event of a loss of power to the host system and or the data storage controller.

Abstract: A luminaire having a housing with a column extending therefrom and a bracket secured to the column, the bracket having a body and two wings extending from opposing sides of the body, at least a portion of each wing extending in a direction at least partially away from the column. The mounting bracket allows installation of the luminaire to a structure, such as a ceiling or canopy, by inserting the luminaire column and bracket into an aperture in the structure from the underside of the structure. The aperture edge forces the wings to flex inward as the column advances through the aperture until the wings pass the aperture edge and spring outward to hold the luminaire to the structure. The mounting bracket thus facilitates quick attachment of the luminaire to the structure and allows attachment of additional mounting hardware to further secure the luminaire to the structure.

Abstract: A charging system is provided. The charging system includes: a charging stand for obtaining vehicle information from the vehicle and transmitting the obtained vehicle information to a management server, and supplying power to a battery equipped in the vehicle on the basis of the transmitted vehicle information; and the management server for determining a charging condition of the battery equipped in the vehicle by using the vehicle information transmitted through the charging stand, and transmitting charging information corresponding to the determined charging condition to the charging stand.

Abstract: Methods and apparatus are provided for communicating pseudo-orthogonal pilot tones in a multiple antenna communication system. Data is transmitted in a multiple antenna communication system having N transmit antennas by generating a number of pilot tones for each of the N transmit antennas, wherein the pilot tones for each of the N transmit antennas are pseudo-orthogonal with each other; and transmitting the data on each of the N transmit antennas. The pilot tones are generally embedded in the data. Data is received in a multiple antenna communication system having N transmit antennas by receiving the data on each of the N transmit antennas, wherein the data includes a number of pilot tones for each of the N transmit antennas, wherein the pilot tones for each of the N transmit antennas are pseudo-orthogonal with each other. The pilot tones can be orthogonal in the frequency domain, time domain, spatial domain, or all of them.

Abstract: Provided is a data transfer apparatus according to an embodiment of the present invention including: a power supply unit supplying operation power; a communication unit connected with an external apparatus and downloading inverter control data from the external apparatus; a memory storing the inverter control data downloaded by the communication unit; a connection unit connected to an inverter, transferring the inverter control data stored in the memory to the inverter, and supplying the operation power supplied through the power supply unit to the inverter; and a control unit allowing the operation power to be supplied to the inverter and allowing the inverter control data to be transferred to the inverter whenever the inverter is connected.

Abstract: A light-emitting diode (LED) apparatus comprises a substrate, a first layer formed over at least a portion of the substrate, an active layer formed over at least a portion of the first layer, a second layer formed over at least a portion of the active layer, and at least one waveguide formed below the substrate. A first portion of light from the LED is directed in a first direction and a second portion of light from the LED is directed in a second direction via the waveguide, the second direction being different than the first direction. The apparatus may further comprise a shutter formed at least one of above and below the waveguide, the shutter being adjustable to control an amount of light entering or exiting the waveguide.

Abstract: Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.

Abstract: Sliding-window based data processing includes receiving an analog signal, converting the analog signal to a series of digital samples synchronous to a sampling clock, performing a first discrete Fourier transform on a first portion of the series of digital samples, performing a second discrete Fourier transform on a second portion of the series of digital samples, performing a third discrete Fourier transform on a third portion of the series of digital samples, generating a first series of zero phase start values by calculating a zero phase start value based on the first discrete Fourier transform in a sliding-window at a series of time increments across the servo preamble, storing the zero phase start values, and averaging the stored zero phase start values at the end of the servo preamble.

Abstract: A method of designing a circuit, an apparatus and a structural analysis tool are disclosed. In one embodiment, the structural analysis tool includes: (1) a structural analyzer configured to apply a structural rule to the circuit design in a design environment of said design process having valid timing data and (2) a structural assessor configured to generate structural data of the circuit design based on application of the structural rule by the structural analyzer.

Abstract: Described embodiments provide a multi-port memory system that has a plurality of memory banks and an equal number of mapping memory banks, each one of the data memory banks corresponding to one of the mapping memory banks. The multi-port memory reads, from one of the mapping memory banks selected by a read logical bank number, a read physical bank number identifying which one of the data memory banks data is to be read. The memory system also calculates, from at least one physical bank number read from the mapping memory banks other than the mapping memory bank selected by the read logical bank number, a write physical bank number indicating which one of the data memory banks is to be written. The calculation uses a hash of the physical bank numbers, such as by using an Exclusive-OR. This arrangement allows for simultaneous read/write access of the memory with fixed latency.

Abstract: A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and quadrature local oscillator signals with a local oscillator frequency of at least about 5 MHz. The local oscillator frequency varies between a selectable minimum frequency and a selectable maximum frequency. The first mixer is configured to mix a fixed frequency clock signal with the in-phase local oscillator signal to output a first mixer output. The second mixer is configured to mix the fixed frequency clock signal with the quadrature local oscillator signal to output a second mixer output. An adder is configured to add the first and second mixer outputs to produce a frequency-modulated clock signal with a frequency that is about the sum of the fixed frequency and the local oscillator frequency and includes a periodic jitter.

Abstract: Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller, wherein the broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein the combined snoop response is a combination of at least one snoop response from a plurality of cache controllers; receives broadcast cache line data from a source cache as instructed by the bus controller for the entry during a data phase; and processes a subsequent cache transaction CTR2 for the entry based on one or more of the broadcast combined snoop response and the broadcast cache line data.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.