Abstract: A temperature measurement apparatus using a negative temperature coefficient (NTC) thermister is provided. A temperature sensor includes the NTC thermister and a variable resistor part, in which a resistance value of the variable resistor part varies between a first resistance value for a first output voltage value and a second resistance value for a second output voltage value to allow a voltage value corresponding to a present temperature to be outputted. A voltage temperature matching unit outputs the present temperature based on the first output voltage value and the second output voltage value.
Type:
Application
Filed:
August 25, 2014
Publication date:
March 5, 2015
Applicant:
LSIS CO., LTD.
Inventors:
Ho Sang JIN, Chun Suk YANG, Jae Ho LEE, Chan Gi PARK
Abstract: The protecting relay may include: an input conversion unit configured to receive the analog signal and sample the analog signal according to a pre-set sampling period; a multiplexer configured to selectively output any one of a plurality of signals output from the input conversion unit; a programmable gain amplifier (PGA) configured to set different gain values according to signals output from the multiplexer, and amplify a signal output from the multiplexer with a pre-set gain value; an analog-to-digital converter (ADC) configured to convert an analog signal output from the PGA into a digital signal; and a controller configured to determine whether the analog signal received through the input conversion unit includes a surge signal based on the plurality of sampled data which have been converted into the digital signal, and determine whether to perform a relay function based on the determination results.
Abstract: The disclosure is directed to a system and method of a system and method for determining fundamental bit cell duration of a data record, which can be used for pattern-dependent write (PDW) current control. According to various embodiments of the disclosure, at least a first portion of a data record is fed through a plurality of delay units. A binary output of each delay unit is stored in at least one register when the delay units have received the first portion of the data record. The register contents are then decoded to determine fundamental bit cell duration of the data record based upon the stored binary outputs.
Abstract: A first communication device calculates a plurality of data error codes for detecting an error in a plurality of data fields by using the plurality of data fields. The first communication device generates a packet comprising the plurality of data fields and the plurality of data error codes, and then transmits the packet which is generated to a second communication device.
Type:
Application
Filed:
October 22, 2012
Publication date:
March 5, 2015
Applicant:
LSIS CO., LTD.
Inventors:
Sung Han Lee, Dae Hyun Kwon, Joon Seok Oh
Abstract: The present disclosure relates to an apparatus for updating an OS (Operating System) in PLC (Programmable Logic Controller) configured to update an OS in a PLC, and to perform an operation by instantly applying the updated OS to the PLC, and a method using the same, the apparatus including an MPU (Micro Processing Unit), a flash memory, a second working memory, and a switching unit.
Abstract: Disclosed is a data sharing system between a master inverter and a slave inverter, in which input/output ports between the master inverter and the slave inverter are selectively shared through background communication through Controller Area Network communication. In a data sharing system in which input/output devices between a mater inverter and a slave inverter are shared, the master inverter determines the presence of outputting output data through the slave inverter, based on information on the presence of sharing a slave input/output device included in the slave inverter.
Abstract: An apparatus includes a storage device and a host device. The storage device may be configured to encrypt and decrypt user data during write and read operations, respectively. The host device is communicatively coupled to the storage device. The host device may be configured to execute the write and read operations by concentrating a first number of virtual bands into a second number of real bands, wherein said second number is smaller than said first number.
Abstract: Disclosed is an event communication apparatus for a protection relay, which effectively simplifies an event determination operation by a main processing module and a communication module, thereby enhancing updating. The event communication apparatus for the protection relay includes a shared memory configured to store and provide data needed to share, a main processing module configured to, whenever an event occurs, update previous event data to a status information of the event and a status occurrence time information as new event data, and write the updated event data into the shared memory, and a communication module configured to periodically read status information from the shared memory, compare the read status information with pre-stored previous status information to determine whether there is a status change, determine occurrence of a new event when there is the status change, and transmit corresponding event data to an supervisory monitor immediately when the new event occurs.
Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for tone reduction in relation to data transmission.
Type:
Application
Filed:
September 12, 2013
Publication date:
March 5, 2015
Applicant:
LSI Corporation
Inventors:
Nayak Ratnakar Aravind, Bruce A. Wilson, Lu Pan, Haitao Xia
Abstract: A magnetic recording system includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a quadrature amplitude modulator operable to combine the analog signals to yield a quadrature amplitude modulated signal, a quadrature amplitude demodulator operable to yield a plurality of demodulated signals from the quadrature amplitude modulated signal corresponding to each channel of the array, and a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.
Type:
Application
Filed:
October 8, 2013
Publication date:
March 5, 2015
Applicant:
LSI Corporation
Inventors:
George Mathew, Angelo R. Mastrocola, Robert A. Greene
Abstract: A hard disk drive uses a second, reference burst field in a preamble to estimate burst phase and burst magnitude. Such estimations are used for position error signal integration and repeatable runout correction. Gain error is also derived from such estimations. Information contained in a preamble field is used in conjunction with the reference burst phase estimation to synchronize servo address marks.
Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reducing inter-track interference in relation to processing data retrieved from a storage medium.
Type:
Grant
Filed:
October 24, 2013
Date of Patent:
March 3, 2015
Assignee:
LSI Corporation
Inventors:
Eui Seok Hwang, Jongseung Park, Ivana Djurdjevic, Richard Rauschmayer
Abstract: An inverter according to an embodiment of the present disclosure may include a converter having a switch, configured to convert a DC voltage into a half-wave rectified sine waveform voltage; a switching device unit having a switch, configured to convert the half-wave rectified sine waveform voltage into a sine waveform voltage; and a controller configured to control the on/off of the switch of the converter and the switch of the switching device unit.
Abstract: An output current distortion compensating apparatus in an inverter is disclosed, the inverter including an inverter controller generating a PWM signal for controlling a PWM voltage generator, wherein the inverter controller includes a first dead time compensation voltage generator generating a compensation voltage based on an output current polarity of each phase in the inverter, and a second dead time compensation voltage generator generating a compensation voltage based on an output current waveform of each phase in the inverter, and wherein a first dead time compensation voltage outputted from the first dead time compensation voltage generator and a second dead time compensation voltage outputted from the second dead time compensation voltage generator are added to generate a final dead time compensation voltage, thereby preventing occurrence of hunting phenomenon in which a current is greatly fluctuated.
Abstract: Provided is an apparatus for controlling speed in induction motor in which tension command and friction loss compensation are used to calculate a torque limit relative to an output of a speed controller, which is then used to limit the speed of the induction motor, whereby a tension sensor and a position sensor are not used in the continuous processing line to improve performance of the vector control type induction motor.
Abstract: Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component codeword; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the bit error count and the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword.
Type:
Grant
Filed:
September 4, 2012
Date of Patent:
March 3, 2015
Assignee:
LSI Corporation
Inventors:
Ngok Ning Chu, Lei Chen, Herjen Wang, Johnson Yen
Abstract: Provided are a method for compensating instantaneous power failure in medium voltage inverter and a medium voltage inverter system by using the same, the method for compensating instantaneous power failure in medium voltage inverter including a plurality of power cells supplying a phase voltage to a motor by being connected to the motor in series, the method including decreasing an output frequency of the plurality of power cells by as much as a predetermined value at a relevant point where an input voltage of the plurality of power cells is less than a reference value, decreasing the output frequency at a predetermined deceleration gradient, and maintaining the output frequency during restoration of input voltage as long as a predetermined time, in a case the input voltage is restored.
Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular case, a system is disclosed that includes a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock, and a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock, and an idle time enforcement circuit operable to modify an average frequency of at least one of the first clock and the second clock.
Abstract: In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.
Type:
Grant
Filed:
February 19, 2014
Date of Patent:
March 3, 2015
Assignee:
LSI Corporation
Inventors:
Peter Kiss, Said E. Abdelli, Donald R. Laturell, Ross S. Wilson, James F. MacDonald
Abstract: The disclosure is directed to a system and method of determining signal quality based upon at least one of: a comparison of energy content of the signal to a threshold energy content, a comparison of energy content of the fundamental harmonic of the signal to a specified percentage of the energy content of the signal, and a comparison of a difference between phase of the signal and a target phase to a threshold phase difference.