Abstract: Operations of an electronic device are simulated by generating and executing a bit-accurate model of the device using an input signal having at least one transition that corresponds to a step input having a pre-transition value (e.g., 0 for a positive transition) for a specified duration before the transition and a post-transition value (e.g., 1 for a positive transition) for a specified duration after the transition. The corresponding step-response results are differentiated with respect to time to generate impulse-response results for the device. The impulse-response results are converted into the frequency domain to determine frequency-domain characteristics of the device that are used to generate a statistical model of the device, which can be executed to simulate all operations of the device, include low bit-error-rate (BER) simulations that would take too long to simulate using the bit-accurate model.

Abstract: Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

Abstract: Methods and structure for improved flexibility in managing cache memory in a storage controller of a computing device on which multiple virtual machines (VMs) are operating in a VM computing environment. Embodiments hereof provide for the storage controller to receive configuration information from a VM management system coupled with the storage controller where the configuration information comprises information regarding each VM presently operating on the computing device. Based on the configuration information, the storage controller allocates and de-allocates segments of the cache memory of the storage controller for use by the various virtual machines presently operating on the computing device. The configuration information may comprise indicia of the number of VMs presently operating as well as performance metric threshold configuration information to allocate/de-allocate segments based on present performance of each virtual machine.

Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly, and more particularly to data processing relying on efficiency improved data detection.

Abstract: Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.

Abstract: A method of generating length parameters, comprising the steps of reading a data stream from a host, detecting a particular field of the data stream, and calculating a variable based on a length parameter of a first list to be transferred. The data stream may comprise a plurality of definitions. The method may also comprise the step of selecting one of the list definitions. One of the list definitions may be used to generate a length parameter used in a second list in response to (i) the particular field of the data stream and (ii) the length parameter of the first list.

Abstract: In one embodiment, a simulator, e.g., for a hard-disk drive selects for testing a signal-to-noise ratio (SNR) value from a range of ratios and an error-correction codeword pattern from a range of codeword patterns. The simulator simulates a communications channel by applying write noise, inter-symbol interference, and read noise to the codeword pattern to generate a noisy signal. In addition, the simulator adds arbitrary-noise to the codeword to accelerate the speed of the simulation. The arbitrary noise increases the probability of converging on a trapping set and does not represent any noise introduced by the communications channel. The simulator attempts to decode the noisy signal, and if decoding is unsuccessful, then the simulator increments an error counter corresponding to the selected signal-to-noise ratio. This process is repeated for all possible combinations of signal-to-noise ratio values and codeword patterns to determine the error rate for all of the signal-to-noise ratio values.

Abstract: The present invention provides an HDD performance enhancement system that utilizes excess disk capacity as cache memory to enhance the I/O performance of the drive. The cache memory is distributed throughout the disk, for example in alternating tracks, sectors dedicated to serving as cache, or other distributed cache track segments or segment groups. Distributing the cache throughout the disk reduces the physical distance of the I/O head to the closest available cache location. The system minimizes the write seek time by storing write data in the closest available cache location. High utilization data blocks are stored in multiple cache location locations to reduce read seek time for high utilization data. The cached data is eventually written to permanent memory and cleared from the cache during idle or low data storage utilization periods.

Abstract: Methods and structure are provided for enhancing zone configuration processes in a Serial Attached SCSI (SAS) architecture. The method includes embedding, at a SAS initiator, a ZONE UNLOCK request within a Serial Management Protocol (SMP) ZONE ACTIVATE command. The method also comprises transmitting the SMP ZONE ACTIVATE command to a SAS expander, and receiving, at the SAS expander, the SMP ZONE ACTIVATE command. Further, the method includes detecting, at the SAS expander, the ZONE UNLOCK request within the SMP ZONE ACTIVATE COMMAND. Additionally, the method includes copying, at the SAS expander, shadow SAS zoning data from a memory of the expander to current SAS zoning data at the memory of the expander responsive to acquiring the SMP ZONE ACTIVATE command. The method also comprises unlocking the SAS expander responsive to extracting the ZONE UNLOCK request from the SMP ZONE ACTIVATE command.

Abstract: An apparatus comprises a clock generator, first and second memory drivers and a multiple-port memory device having at least first and second ports configured to receive input signals from and supply output signals to respective ones of the first and second memory drivers, the multiple-port memory device further comprising a single-port memory device and control circuitry coupled between the first and second ports and the single port of the single-port memory device. The clock generator generates first and second clock signals having respective first and second clock rates, the clock rate of the second clock signal being an integer multiple of the clock rate of the first clock signal. The first and second memory drivers are configured to operate using the first clock signal at the first clock rate, and the single-port memory device is configured to operate using the second clock signal at the second clock rate.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: a buffer circuit, an equalizer circuit, a data processing circuit, and a retry determination circuit. The buffer is operable to store digital samples as a buffered output, and the equalizer circuit is operable to equalize the buffered output using a first equalization target to yield a first equalized output, and to yield a second equalized output using a second equalization target. The retry determination circuit is operable to select the second equalization target based at least in part on an occurrence of an error.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system.

Abstract: Lighting systems, apparatus, and methods are disclosed, which employ optical transmission of two-dimensional control signals to manipulate lighting elements. The lighting apparatus can include a projector with an IR LED array to wirelessly transmit pixel information onto a target space. The pixel information controls lighting elements within the target space. The two-dimensional control signals can includes subareas corresponding to lighting elements in a control array. The lighting elements can be lights producing light of desired wavelengths including infrared and/or visible wavelengths. LEDs can be used as light sources in exemplary embodiments.

Abstract: A method and/or a system of unified management of a hardware interface framework is disclosed. In one embodiment, a method of the hardware interface framework includes applying to a client interface module with a generic agent module agnostic to a change in a device coupled to the hardware interface framework and a change in a management module and communicating a management data of the management module between the client interface module and a server interface module coupled to the device using the generic agent module. The method may also include synchronously communicating a request data of the management module to collect a response data of the device and asynchronously communicating an event data of an adapter module to the management module.

Abstract: Described embodiments provide for detection and selection by the user of a ticker region within a first video broadcast; and copying and overlaying the detected and selected ticker region over a second video broadcast. Motion estimation techniques are employed to identify the ticker region location and associated borders of the ticker region. The streaming video corresponding to the ticker region is buffered. Some embodiments allow for post-processing of the overlayed ticker region to, for example, eliminate artifacts of, match resolution to, and match aspect ratio of the overlayed ticker region to the second video broadcast.

Abstract: Various embodiments of the present invention provide systems and methods for detecting contact. For example, a method for detecting head contact is disclosed that includes: receiving an interface signal operable to indicate a physical contact between a sensing device and a storage medium; band pass filtering a data set derived from the interface signal to yield a band pass filtered output; comparing the band pass filtered output to a level threshold to yield a comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; and comparing the aggregated value to an aggregate threshold to yield a contact output.

Abstract: An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences.

Abstract: Various embodiments of the present invention provide systems and methods for data filter tuning. As an example, a method for filter tuning is disclosed that includes: providing a tunable filter having an operation filter and a calibration filter; applying a low frequency test input to the operation filter in place of an input signal to yield a first filter output; calculating a low frequency magnitude value corresponding to the first filter output; applying a high frequency test input to the operation filter in place of an input signal to yield a second filter output; calculating a high frequency magnitude value corresponding to the second filter output; modifying a tuning factor of the calibration filter when a ratio of the high frequency magnitude value and the low frequency magnitude value is outside of a defined range; and storing the tuning factor of the calibration filter when the ratio of the high frequency magnitude value and the low frequency magnitude value is within the defined range.

Abstract: A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation. In one embodiment, a system includes a first group of clock gating cells configured to receive an input clock signal and a first group of flip-flops coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells configured to receive the input clock signal, and a second group of flip-flops coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element to delay the input clock signal by a second duration during the scan shift operation.