Abstract: A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation. In one embodiment, a system includes a first group of clock gating cells configured to receive an input clock signal and a first group of flip-flops coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells configured to receive the input clock signal, and a second group of flip-flops coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element to delay the input clock signal by a second duration during the scan shift operation.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline of the memory device, and the second switching circuitry being controlled using the wordline and a complemented bitline of the memory device.

Abstract: Methods and systems for reducing the signal path count between circuits within a SAS expander used for establishing SAS connections. The system comprises a SAS expander. The SAS expander comprises a plurality of link layer control circuits, each link layer control circuit adapted to communicatively couple with a SAS device. The SAS expander further comprises a connection manager communicatively coupled with the link layer control circuits for routing communications between the link layer control circuits. Each of the plurality of link layer control circuits is adapted to establish a SAS connection with another link layer control circuit through the connection manager by segmenting a plurality of interconnect signals into multiple data segments for sequential transmission to the connection manager, (e.g., without impacting the performance of the connection manager). The connection manager interprets the data segments to extract the plurality of interconnect signals to establish the SAS connection.

Abstract: The present inventions are related to systems and methods for transferring information to and from a storage medium, and more particularly to systems and methods for positioning a sensor in relation to a storage medium. For example, an apparatus for determining a sensor position is disclosed that includes discrete Fourier transform calculators operable to process input data to yield a magnitude response of the input data at each of a number of candidate frequencies, a comparator operable to compare the magnitude responses to yield a winning candidate frequency, a servo controller operable to process at least one servo field in the input data to identify a position of a sensor based on the at least one servo field, and a servo frequency synthesizer operable to establish a frequency of operation in the servo controller based at least in part on the winning candidate frequency.

Abstract: A method for dynamic storage tiering may include, but is not limited to: receiving an input/output (I/O) request from a host device; determining whether the I/O request results in a cache hit; and relocating data associated with the I/O request between a higher-performance storage device and lower-performance storage device according to the determination whether the data associated with the I/O request is stored in a cache.

Abstract: Techniques are disclosed for performing branch metric computations/noise predictive calibration/adaptation for over-sampled Y samples. In one or more embodiments, the techniques employ a data processing apparatus (circuit) that includes a parallel to serial convertor configured to receive a first stream of sample data (e.g., Y samples) and a second stream of sample data (e.g., Z samples). The parallel to serial convertor is operable to combine the first stream of sample data and the second stream of sample data into a combined stream of sample data (e.g., combined Y and Z samples). The data processing apparatus (circuit) further includes a filter (e.g., a noise predictive finite impulse response (NPFIR) filter, a noise whitening filter, such as a noise predictive calibration/adaptation module (NPCAL) filter, and so forth) that is configured to receive the combined stream of sample data and whiten noise in the combined stream of sample data.

Abstract: Various embodiments of the present invention provide apparatuses, systems and methods for data detection in a detector with a pruning control system. For example, a data detector is disclosed that includes a first set of counters operable to distinguish prunable data from non-prunable data in the data detector, a second set of counters operable to generate initial values for the first set of counters, and a prune control signal generator operable to generate a prune control signal based on the first set of counters. The second set of counters is operable to generate the initial values at least in part before a syncmark is detected in a data sector. The initial values are used to initialize the first set of counters when the syncmark is detected in the data sector. The prune control signal controls whether the data detector is allowed to prune a trellis.

Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.

Abstract: A method of determining signal routing in an integrated circuit includes providing first coordinates of an input/output cell and second coordinates of an input/output pad to a parametric routing module. The parametric routing module receives at least one wire path parameter. The parametric routing module uses the at least one connection path parameter to determine a physical dimension of a wire path between the first coordinates and the second coordinates.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

Abstract: In one embodiment, a heterogeneous multi-processor computer system includes (i) a plurality of dedicated processors (DPs), each DP configured to implement one or more program modules during runtime operations; (ii) two or more control processors (CPs), each CP configured to run scheduling software for controlling the runtime operations by a corresponding subset of DPs; and (iii) one or more buses interconnecting the DPs and CPs. Each CP is configured to vary timing of implementation of the program modules for the corresponding subset of DPs based on resource availability, and each CP is configured to vary timing of data transfers by the corresponding subset of DPs based on resource availability.

Abstract: A method for mapping addresses between one or more master devices and at least one common slave device in a multiprocessor system is provided, the system including a bus interconnect for interfacing between the master devices and the common slave device. The method includes steps of: receiving a first address corresponding to a bus transaction between a given one of the one or more master devices and the common slave device; decoding a unique identifier associated with the given one of the one or more master devices; and generating a second address as a function of the first address and the unique identifier for remapping access to the common slave device by the given one of the one or more master devices.

Abstract: A sensing circuit for use in a memory including memory cells and at least one bitline coupled with the memory cells includes first and second sense amplifiers and a controller coupled with the sense amplifiers. The first sense amplifier is adapted to read a selected one of the memory cells coupled to the first sense amplifier via a corresponding bitline. The second sense amplifier is adapted to read a selected one of the memory cells coupled to the second sense amplifier via a corresponding bitline. The controller selectively connects one of the first and second sense amplifiers in an active path of the memory in a manner which enables one of the sense amplifiers to be operative in a precharge mode and another of the sense amplifiers to be concurrently operative in a sensing mode during a given memory cycle.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors. The system comprising a plurality of processors of two or more different processor types. Machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution. A Source Code Generator (SCG) integrates scheduling information for the selected schedule solution into the scheduling software for a first processor such that the scheduling information is compiled with the scheduling software.

Abstract: Disclosed is a method of storage tiering with minimal use of DRAM memory for header overhead that utilizes the beginning of the volume to store frequently accessed or hot data. A solid state storage device is placed at the beginning of a tiered volume and is used to store frequently accessed data. When data becomes less frequently accessed it is moved to a cold data storage area on a hard disk drive in the tiered volume. The data exchange is performed on a one-to-one basis reducing the amount and use of DRAM.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal oscillating at a frequency in response to a first control signal and a second control signal. The second circuit may be configured to generate the second control signal in response to (i) an input voltage and (ii) the output signal. The second circuit (i) generates the second control signal by comparing a peak voltage of the output signal to the input voltage and (ii) adjusts an amplitude of the control signal in response to the comparison.

Abstract: An apparatus generally having a port, a first circuit and a second circuit is disclosed. The port may be configured to receive a current length of a codeword. The current length may be less than a maximum length of the codeword that the apparatus is designed to decode. The first circuit may be configured to calculate in parallel (i) a sequence of intermediate syndromes from the codeword and (ii) a sequence of correction values based on the current length. The second circuit may be configured to generate a particular number of updated syndromes by modifying the intermediate syndromes with the correction values. The particular number is generally twice a maximum error limit of the codeword.

Abstract: Methods and system for implementing a clustered storage solution are provided. One embodiment is a storage controller that communicatively couples a host system with a storage device. The storage controller comprises an interface and a control unit. The interface is operable to communicate with the storage device. The control unit is operable to identify ownership information for a storage device, and to determine if the storage controller is authorized to access the storage device based on the ownership information. The storage controller is operable to indicate the existence of the storage device to the host system if the storage controller is authorized, and operable to hide the existence of the storage device from the host system if the storage controller is not authorized.

Abstract: Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed.

Abstract: In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual soft-output values of the at least two subsets are interleaved with one another. Local de-interleaving is performed on each set such that the soft-output values of each subset are grouped together. Global de-interleaving is then performed on the subsets such that the subsets corresponding to the same block columns of the H-matrix are arranged together. In another embodiment, an interleaver performs global then local interleaving to perform the inverse of the de-interleaver processing.