Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a plurality of packed items by extracting-and-packing a plurality of input data words based on a bit mask. The second circuit may be configured to (i) receive the packed items from the first circuit, (ii) sequentially buffer the packed items in a plurality of registers, at least one of the packed items crossing a boundary between a current one of the registers and a next one of the registers, and (iii) write the packed items in the current register to a memory in response to the current register becoming full.

Abstract: Described embodiments provide a wireless communication system that employs modulation and precoding. An input bit stream is divided into one or more batches. Each batch has a consecutive number of bits. A modulation scheme is determined for batches. A precoding scheme for layer mapping is determined for the batches. Based on the modulation scheme and precoding scheme, a look-up table (LUT) is selected. The selected LUT maps the batches into one or more modulated and precoded layers. The modulated and precoded batches are provided to a transmission module.

Abstract: In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) each CNU is configured to operate in the second mode to generate averaged R messages, and (iii) the decoder attempts to recover the correct codeword using the averaged R messages. Averaging the R messages may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.

Abstract: Methods and apparatus are provided for burst transfers of data between DDR memories and embedded processors during training of the PHY interface in an embedded system. An embedded system comprises an embedded processor having at least one cache controller; a memory, wherein the memory has an atomic memory access that comprises a plurality of clock edges; and a memory controller having a physical interface to convert digital signals between the embedded processor and the memory, wherein the cache controller executes a training process to determine a delay through the physical interface for each of the plurality of clock edges using a burst transfer of data. The burst transfer comprises reading a data pattern from the memory and storing the data pattern in one or more registers in the embedded processor.

Abstract: A mobile communications device Includes at least two long-range wireless Communications engines. Each long-range wireless communications engines includes a respectively different communications protocol stack, for receiving or transmitting first long-range wireless communications signals using a first long-range communications protocol simultaneously while receiving or transmitting second long-range wireless communications signals using a second long-range communications protocol At least two radio frequency blocks are provided, for receiving or transmitting the first long-range wireless signals simultaneously while receiving or transmitting the second long-range wireless signals. A user interface is provided for inputting and outputting user data Io and from the at least two long-range wireless communications engines, respectively.

Abstract: An apparatus comprising a first core of a multi-core processor, a second core of a multi-core processor and a bus matrix. The first core may be configured to communicate through a first input/output port. The first core may also be configured to initiate a testing application. The second core may be configured to communicate through a second input/output port. The second core may also be configured to respond to the testing application. The bus matrix may be connected to the first input/output port and the second input/output port. The bus matrix may transfer data between the first core and the second core. The testing application may generate real-time statistics related to the execution of instructions by the second core.

Abstract: Various embodiments of the present invention provide apparatuses and methods for processing data in an oversampled data processing circuit with multiple detectors. For example, an apparatus for processing data is disclosed that includes a first analog to digital converter operable to sample a continuous signal at a first sampling phase to yield a first digital output, a second analog to digital converter operable to sample the continuous signal at a second sampling phase to yield a second digital output, wherein the second sampling phase is different from the first sampling phase, a first detector operable to process the first digital output to yield a first detector output, and a second detector operable to process the second digital output and the first detector output to yield a detected output.

Abstract: Methods and structure for accounting are provided for enhancing communications via a PCIE bridge. The bridge comprises a host interface that manages communications with a host device, and a PCIE interface that provides Memory Read Requests (MRds) to a PCIE device and receives Memory Read Completions (MRCs) from the PCIE device. The bridge also comprises a control unit that inserts tag information into the MRds. The control unit detects a reset of the host interface and revises the tag information inserted into the MRds responsive to detecting the reset. Additionally, the control unit analyzes tag information of received MRCs to determine whether it is the revised tag information or is old tag information, returns completion data from MRCs having the revised tag information to the host device, and discards completion data from received MRCs having the old tag information.

Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell.

Abstract: A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

Abstract: Methods and structure are provided for implementing security features in SCSI Enclosure Services (SES) systems. The system comprises an SES device server, which includes a frontend interface, control unit, and backend interface. The frontend interface is operable to receive SES commands generated by Small Computer System Interface (SCSI) devices, and the backend interface is operable to manage operations of at least one peripheral device communicatively coupled with the SES device server based on received SES commands. The control unit is operable to determine whether a SCSI initiator that generated an SES command is an authorized device. The control unit is further operable to perform the SES command in response to determining that the SCSI initiator is an authorized device, and is further operable to reject the SES command in response to determining that the SCSI initiator is not an authorized device.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: An electronic storage device includes a bit cell circuit, feedback circuit, and read accelerator circuit. The bit cell circuit is adapted for connection with true and complementary bit lines. The feedback circuit includes a first transistor which is coupled to a first voltage potential and responsive to the complementary bit line. The read accelerator circuit includes second, third, and fourth transistors coupled between the feedback circuit and a second voltage potential. The second transistor is responsive to a read line, the third transistor is responsive to the true bit line, and the fourth transistor is responsive to the complementary bit line. The read accelerator circuit is configured to provide a discharge path for at least one of the true bit line and the complementary bit line during a read access of the bit cell. Embodiments of a corresponding electronic read access accelerator device and method are also provided.

Abstract: Techniques are described for increasing a lifetime of a plurality of blocks of memory by equalizing a variation between the blocks. In operation, blocks to be written are allocated from a set of blocks having a lifetime factor below a threshold. The threshold is reset as required to resupply the set of blocks available for allocation.

Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

Abstract: Methods and apparatus are provided for trellis-based modulation encoding. A signal is modulation encoded by encoding one or more blocks of the signal using one or more corresponding edges in a trellis, wherein each edge in the trellis has a corresponding bit pattern; selecting a winning path through the trellis based on at least one transition-based run-length constraint; and generating an encoded sequence using edges associated with the winning path. Exemplary trellis pruning techniques are also provided. The winning path through the trellis is selected by minimizing one or more modulation metrics.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: An apparatus comprising a controller, one or more host devices and one or more storage devices. The controller may be configured to store and/or retrieve data in response to one or more input/output requests. The one or more host devices may be configured to present the input/output requests. The one or more storage devices may be configured to store and/or retrieve the data. The controller may include a cache memory configured to store the input/output requests. The cache memory may be configured as a memory allocation table to store and/or retrieve a compressed version of a portion of the data in response to one or more network parameters. The compressed version may be retrieved from the memory allocation table instead of the storage devices based on the input/output requests to improve overall storage throughput.

Abstract: In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.

Abstract: A memory management apparatus includes a first controller adapted to receive an input data sequence including one or more data frames and operative: to separate each of the data frames into a payload data portion and a header portion; to store the payload data portion in at least one available memory location in a physical storage space; and to store in a logical storage space the header portion along with at least one associated index indicating where in the physical storage space the corresponding payload data portion resides. The apparatus further includes a second controller operative, as a function of a data read request, to access the physical storage space using the header portion and associated index from the logical storage space to retrieve the corresponding payload data portion and to combine the header portion with the payload data portion to generate a response to the data read request.