Patents Assigned to LSI
  • Crossing ISI cancellation
    Patent number: 8611482
    Abstract: An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventor: Lizhi Zhong
  • System optimization using soft receiver masking technique
    Patent number: 8611406
    Abstract: Communication system optimization using a soft receiver masking technique is disclosed. For example, a method for testing a communication device comprises obtaining a software representation of a receiver portion of a given communication device. A data signal received from a transmitter through a given link channel is then processed, wherein the processing step is performed using the software representation of the receiver portion of the communication device. An output signal is caused to be generated by the software representation of the receiver portion. An eye mask test is then applied to the output signal. Based on a result of the eye mask test, one or more parameters of the transmitter may be adjusted.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Xingdong Dai, Max J. Olsen, Scott A. Werner, Geoffrey Zhang
  • Optical source driver circuit with controllable termination
    Patent number: 8611385
    Abstract: A driver circuit for a laser diode or other optical source comprises a controllable termination for a transmission line coupled between the driver circuit and the optical source, with the controllable termination being switchable between at least first and second termination configurations. The transmission line comprises a first conductor coupled to a first terminal of the optical source and a second conductor coupled to a second terminal of the optical source, and the driver circuit comprises a first current source configured to drive the first conductor, and a second current source configured to drive the second conductor. By way of example, the first termination configuration may comprise an alternating current (AC) termination configuration and the second termination configuration may comprise a direct current (DC) termination configuration.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventor: Jason P. Brenden
  • Systems and methods for selective decoder input data processing
    Patent number: 8611033
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a data decoder circuit, and a multi-path circuit. The data detector circuit is operable to apply a data detection algorithm to a data input and a decoder output to yield a detected output. The data decoder circuit is operable to apply a decoding algorithm to a decoder input to yield the decoder output and a status input. The multi-path circuit is operable to provide the decoder input based at least in part on the detected output and the status input.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Zongwang Li, Fan Zhang, Wu Chang, Shaohua Yang
  • Split decode latch with shared feedback
    Patent number: 8610461
    Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) an intermediate signal, and (ii) a clock signal. The second circuit may be configured to generate the intermediate signal and a digital complement of the output signal in response to (i) an input signal and (ii) the clock signal. The intermediate signal may form a feedback to ensure the output signal and the digital complement of the output signal are in complementary states during a power up.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Richard J. Stephani, Amy R. Rittenhouse, Donald A. Evans
  • Systems and methods for qualitative media defect determination
    Patent number: 8612843
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a media defect detector circuit. The media defect detector circuit is operable to compare a data input derived from a medium against at least a first defect level to yield a first level output, and a second defect level to yield a second level output; and provide a combination of the first level output and the second level output as a defect quality output. A value of the defect quality output corresponds to a likelihood of a defect of the medium.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Ming Jin, Haitao Xia, Lei Chen
  • Lighting apparatus with a boost
    Patent number: 8608335
    Abstract: Lighting apparatus and structures are described to space electrical drivers from a light panel. In this way, a driver box housing the driver can be spaced from the light panel to communicate with pre-existing facilities (e.g. electrical wiring) and can serve the additional advantage of keeping the driver box out of standing water that may accumulate on the structure.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 17, 2013
    Assignee: LSI Industries, Inc.
    Inventors: Rob Allen Rooms, John D. Boyer
  • Systems and methods for reduced latency loop correction
    Patent number: 8610608
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Nayak Ratnakar Aravind, Scott M. Dziak, Haitao Xia
  • Decoding a progressive JPEG bitstream as a sequentially-predicted hybrid video bitstream
    Patent number: 8611418
    Abstract: An apparatus generally including a first circuit and a second circuit is disclosed. The first circuit may be configured to generate an intermediate bitstream by parsing a Joint Picture Expert Group (JPEG) bitstream carrying a picture. The intermediate bitstream generally includes one or more encoded frames each representing a portion of the picture. The second circuit may be configured to (i) generate one or more intermediate images by decoding the encoded frames and (ii) recreate the picture using the intermediate images.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Kourosh Soroushian, K. Metin Uz, Satish Vithal Joshi
  • Systems and methods for tag information validation in wide port SAS connections
    Patent number: 8612632
    Abstract: Methods and structures for validating tag information received in SAS frames by any of a plurality of ports comprising a SAS wide port. Each port may have a dedicated transport layer processing element. A tag information table is shared by all of the one or more transport layer processing elements. The tag information table is used to store information regarding a particular tag value being valid for use with a particular device and is updated when the particular tag value is no longer valid for use with the particular device. The information is initially stored in response to transmission of a frame that first uses the particular tag value with the particular device. The tag information table is updated to indicate the particular tag value is no longer valid upon receipt of an appropriate SAS frame or by a processing element external to the one or more transport layer processing elements.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Brian A. Day, Srikiran Dravida, Parameshwar Ananth Kadekodi
  • Systems and methods for non-binary LDPC encoding
    Patent number: 8612826
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Zongwang Li, Shaohua Yang, Fan Zhang
  • Techniques For Reducing A Rate Of Data Transfer To At Least A Portion Of Memory
    Publication number: 20130332689
    Abstract: A system, method, and computer program product are provided for reducing a rate of data transfer to at least a portion of memory. In operation, a rate of degradation of at least a portion of memory associated with a drive is determined. Furthermore, a rate of data transfer to the at least a portion of the memory is reduced, based on the determined rate of degradation.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 12, 2013
    Applicant: LSI CORPORATION
    Inventor: Ross John STENFORT
  • METHODS AND APPARTUS FOR PERFORMING POWER ESTIMATION IN CIRCUITS
    Publication number: 20130332142
    Abstract: Power consumption is estimated for an application being executed by a circuit. Power consumption values are estimated for a set of base events executed by the circuit. The application is then reduced to an equivalent sequence of base events selected from the set of base events. Lastly, the estimated power consumption values for the base events in the equivalent sequence of base events are summed.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: LSI CORPORATION
    Inventors: Leonid Lerner, Dmitry Podvalny, Alexander Shinkar
  • POWER-GATED MEMORY DEVICE WITH POWER STATE INDICATION
    Publication number: 20130332763
    Abstract: A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: LSI CORPORATION
    Inventors: Sathappan Palaniappan, Romeshkumar Mehta, Dharmesh Tirthdasani
  • Hardware-based data eye training for high speed links
    Patent number: 8605539
    Abstract: Hardware-based methods and apparatus are provided for training high speed data links used in data transfer applications. A data valid window is calibrated on one or more high speed links by determining an offset delay value for at least one datapath using a finite state machine, wherein the offset delay value is based on a maximum offset delay value and a minimum offset delay value for the at least one datapath; and delaying a read data strobe signal based upon a base delay and the offset delay value for the at least one datapath. The offset delay value can be, for example, an average of the maximum offset delay and the minimum offset delay. The received pattern can be a predefined pattern or a programmable pattern. In addition, the received pattern can cover single-bit transitions and/or multi-bit transitions.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: December 10, 2013
    Assignee: LSI Corporation
    Inventors: Aniruddha Haldar, Srinivas Eppa, Venkatesh Deshpande, Srinivas Vura, Shanmugavel Murugesan
  • Receiver training with cycle slip detection and correction
    Patent number: 8605847
    Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: December 10, 2013
    Assignee: LSI Corporation
    Inventors: Mohammad Mobin, Mark Trafford, Ye Liu, Vladimir Sindalovsky, Amaresh Malipatil
  • Systems and methods for phase compensated harmonic sensing in fly height control
    Patent number: 8605381
    Abstract: Various embodiments of the present invention provide systems and methods for phase compensated harmonic sensing. For example, a circuit for harmonics calculation is disclosed that includes a phase difference estimation circuit and a phase offset compensation circuit. The harmonic calculation circuit is operable to calculate a first harmonic based on a periodic data pattern and a second harmonic based on the periodic data pattern. The phase difference estimation circuit operable to calculate a phase difference between the first harmonic and the second harmonic. The phase offset compensation circuit operable to align the second harmonic with the first harmonic to yield an aligned harmonic.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: December 10, 2013
    Assignee: LSI Corporation
    Inventors: George Mathew, Pradeep Padukone, Hongwei Song, Suharli Tedja
  • Ergonomic, lighted uterine manipulator with cautery
    Patent number: 8603105
    Abstract: A uterine manipulator includes a sound and a body. The sound has a selectively actuatable anchor disposed proximate a distal end and an operating mechanism spaced from the anchor for controlling actuation of the anchor. The body has a passage therethrough adapted to receive the sound passed proximally through the body to a position in which the operating mechanism is accessible proximally of the body and the anchor extends distally.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: December 10, 2013
    Assignee: LSI Solutions, Inc.
    Inventor: Jude S. Sauer
  • Methods and systems for controlling electrical power to DC loads
    Patent number: 8604709
    Abstract: Fixed Frequency, Fixed Duration power controls methods and systems are described for application of power to electrical loads. FFFD techniques according to the present disclosure utilize power train pulses with fixed-frequency fixed-duration pulses to control power applied to a load. The load can be any type of DC load. FFFD techniques allows for controlled variation of the fixed length of the ON pulse, the Fixed length of the OFF or recovery period, the total time period for one cycle, and/or the number of pulses in that time period. Applications to electric motors, electric lighting, and electric heating are described. Related circuits are also described.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: December 10, 2013
    Assignee: LSI Industries, Inc.
    Inventors: Bassam D. Jalbout, Brian Wong
  • Multi-pass routing to reduce crosstalk
    Patent number: 8607180
    Abstract: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: December 10, 2013
    Assignee: LSI Corporation
    Inventor: Anuj Soni