Abstract: A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.

Abstract: A communication system may include a first broadband wireless device and a second broadband wireless device. Signals may be wirelessly communicated from the first broadband wireless device to the second broadband wireless device at a power level that is below a spurious emissions mask. The communicated signals may be transmitted over a designated frequency band. A barrier separates the first broadband wireless device from the second broadband wireless device. The first broadband wireless device may be paired with the second broadband wireless device. Usable channels may be detected within a frequency spectrum band designated for use by the first and the second broadband wireless device. The signals may be wirelessly communicated from the first to the second broadband wireless device via one or more of the detected usable channels. Two or more of the plurality of the detected usable channels may be aggregated and utilized for the communication.

Abstract: Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits.

Abstract: Methods and systems are provided for controlling operations of digital-to-analog converters (DACs), particularly ones comprising multiple DAC elements. In particular, a plurality of DAC elements in a digital-to-analog converter (DAC) may be controlled during digital-to-analog conversions, with the controlling comprising use of a switching arrangement that comprises one or more switching elements configured for controlling switching of each of the plurality of DAC elements. The controlling may comprise forcing one or more of the plurality of DAC elements in the DAC to not switch during the digital-to-analog conversions. Further, the remaining DAC elements may be scrambled. The controlling of the plurality of DAC elements in the DAC may be based on analysis of an input to the DAC that is being converted. The analysis may comprise determining when the input is backed off from full-scale. A switching sequence may be applied, via each of the one or more switching elements.

Abstract: Methods and systems for location determination using structural visual information may comprise receiving global navigation satellite system (GNSS) signals in a wireless device (WD) for determining a first position of the WD. One ore more images of a structure or structures near the WD may be captured and a position may be determined based on a comparison of the structures in the images to structures in a stored database. The database may be pre-stored based on a known future location of a user of the WD. The database may be downloaded and stored when insufficient GNSS signals are present. The database may comprise a plurality of images or may comprise video of structures. A distance from the structures may be determined based on known optical properties of a camera in the WD, and may be used to determine an accurate location based on the images.

Abstract: Methods and systems for an analog crossbar may comprise, in a wireless device comprising a receiver path with an analog crossbar: receiving a digital signal comprising a plurality of channels; amplifying the received signal; converting the amplified signal to an analog signal; separating the analog signal into a plurality of separate channels; routing the plurality of separate channels to desired signal paths utilizing the analog crossbar; and converting the routed plurality of separate channels to a plurality of digital signals. The analog crossbar may comprise an array of complementary metal-oxide semiconductor (CMOS) transistors. The analog crossbar may comprise a plurality of differential pair signal lines, and a plurality of single-ended signal lines. The received signal may be amplified utilizing a low-noise amplifier (LNA), where a gain level of the LNA may be configurable. The analog signal may be separated into separate channels using a channelizer.

Abstract: A low input voltage low impedance termination stage for current inputs may include an output stage for an electrical circuit, the output stage including input cascode transistors and stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor. The input cascode transistors, the feedback transistor, and the stacked output transistors may include complementary metal-oxide semiconductor (CMOS) transistors.

Abstract: A GNSS system operates intermittently and has adaptive activity and sleep time in order to reduce power consumption. The GNSS system provides an enhanced estimate of its position in the absence of GNSS signals of sufficient strength. The user's activity and behavior is modeled and used to improve performance, response time, and power consumption of the GNSS system. The user model is based, in part, on the received GNSS signals, a history of the user's positions, velocity, time, and inputs from other sensors disposed in the GNSS system, as well as data related to the network. During each activity time, the GNSS receiver performs either tracking, or acquisition followed by tracking The GNSS receiver supports both normal acquisition as well as low-power acquisition.

Abstract: A diversity receiver includes a first receiving channel and a second receiving channel. The receiver also includes a baseband processor that computes a difference between the received signal strengths of the signals received from the first and second channels, wherein the processor disables the signal received from the second channel if the difference is greater than a first threshold value and a BER associated with the second receiving channel is greater than a BER threshold value, and disables the signal received from the first channel if the difference is less than the negative first threshold value and the bit error rate (BER) associated with the first channel is greater than the BER threshold value. The receiver further includes a bypass circuit coupled to an input of an amplifier and a RSSI circuit that provides a conduction path between the input and a ground when the RSSI circuit detects a blocker signal.

Abstract: Systems and methods for adjusting timing in a communication system, such as an OFDM system are described. In one implementation an error signal is generated to adjust the timing of a variable rate interpolator so as to adjust FFT timing. The error signal may be based on detection of significant peaks in an estimate of the impulse response of the channel, with the peak locations being tracked over subsequent symbols and the system timing adjusted in response to changes in the peaks.

Abstract: Methods and apparatus for processing multichannel signals in a multichannel receiver are described. In one implementation, a plurality of demodulator circuits may provide a plurality of outputs to a processing module, with the processing module then simultaneously estimating noise characteristics based on the plurality of outputs and generating a common noise estimate based on the plurality of outputs. This common noise estimate may then be provided back the demodulators and used to adjust the demodulation of signals in the plurality of demodulators to improve phase noise performance.

Abstract: A satellite reception assembly that provides satellite television and/or radio service to a customer premises may comprise a wireless interface via which it can communicate with other satellite reception assemblies. Wireless connections between satellite reception assemblies may be utilized for providing satellite content between different satellite customer premises. Wireless connections between satellite reception assemblies may be utilized for offloading traffic from other network connections.

Abstract: A method and an apparatus are provided in an OFDM receiver for detecting and compensating for long echo. The method comprises a first pilot tone interpolation mechanism and a first window placement to filter a received OFDM symbol, a long echo channel detection coupled with a second pilot tone interpolation mechanism, a pre-echo and post-echo detection wherein the pre-echo condition is associated with a second new window placement, and both pre-echo and post-echo conditions place two time windows around a first peak channel response and a second peak channel response for channel estimation. The long echo is estimated by obtaining power spectra of a subset of subcarriers in one OFDM symbol, performing an inverse Fourier transform on the power spectra and determining the long echo by measuring the time between two peaks in the power profile.

Abstract: Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Abstract: Methods and systems for a metal finger capacitor with a triplet repeating sequence incorporating a metal underpass may comprise repeating triplet capacitors integrated on a semiconductor die. The capacitors may comprise a first set of interconnected metal fingers comprising a first terminal of a first capacitor, a second set of interconnected metal fingers comprising a first terminal of a second capacitor, and a third set of interconnected metal fingers comprising a common node that surrounds the first and second sets of interconnected metal fingers. The common node may comprise a second terminal of the capacitors. A repeating pattern of fingers may be: (third set/second set/third set/first set . . . ). The repeating pattern of metal fingers may be arranged in two parallel rows to mitigate variations in the semiconductor die. The interconnected metal fingers may comprise first and second metal layers formed on the semiconductor die.

Abstract: Aspects of a method and system for hybrid redundancy for electronic networks are provided. A first line card may comprise a first instance of a network layer circuit, a first instance of a physical layer circuit, and an interface to a data bus (e.g., an Ethernet bus) for communicating with a second line card. In response to detecting a failure of the first instance of the network layer circuit, the first instance of the physical layer circuit may switch from processing of a signal received via the first instance of the network layer circuit to processing of a signal received via the interface. The system may comprise a second line card. The second line card may comprise a second instance of the network layer circuit. The second instance of the network layer circuit may be coupled to the data bus.

Abstract: A first microwave backhaul transceiver may comprise an antenna array and circuitry. The circuitry may determine misalignment of the first microwave backhaul transceiver, and electronically adjust a radiation pattern of the antenna array to compensate for the determined misalignment of the microwave backhaul transceiver. The circuitry may perform the adjustment of the radiation pattern in real time to compensate for effects of wind on the microwave backhaul transceiver. The circuitry may detect movement of the microwave backhaul transceiver and translate the detected movement into angular misalignment of the radiation pattern of the antenna array. The adjustment of the radiation pattern of the antenna array may comprise an adjustment of a polarization orientation of the antenna array.

Abstract: A communications network comprises performance determination circuitry and link control circuitry. The performance determination circuitry is operable to determine performance of a microwave backhaul link between a first microwave backhaul transceiver and a second microwave backhaul transceiver. The microwave backhaul link backhauls traffic of a mobile access link. The link control circuitry is operable to, in response to an indication from the performance determination circuitry that the performance of the microwave backhaul link has degraded, adjust one or more signaling parameters used for the mobile access link. The link control circuitry is operable to, in response to the indication that the performance of the microwave backhaul link has degraded, adjust one or more signaling parameters used for the backhaul link in combination with the adjustment of the parameter(s) of the access link.

Abstract: A transmitter comprises a local oscillator circuit operable to generate a reference signal, a modulator circuit operable to generate a data-carrying signal using the reference signal, and a test signal generator circuit operable to generate a test signal using the reference signal. The test signal has a first bandwidth, and a test signal insertion circuit is operable to combine the data-carrying signal and the test signal to generate a combined signal. An amount of bandwidth in the combined signal allocated to the test signal is greater than the first bandwidth such that a component of the combined signal corresponding to the test signal is bordered by whitespace. A receiver may then use the test signal to determine and correct for phase noise introduced in the transmitter.

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.