Abstract: Methods and systems for global positioning navigate satellite system configuration of wireless communication applications may comprise in a wireless communication device (WCD) comprising a satellite positioning RF path, determining a location of the WCD utilizing LEO signals received by said satellite positioning RF path, establishing communications with a wireless access point based on the determined location, and configuring a wireless communication function of the WCD based on the determined location. The wireless communication function may comprise a power level of wireless local area network circuitry in the WCD, a point-of-sale transaction, or a synchronization of data on the WCD with one or more devices in a home location of the WCD. The determined location and a transaction ID for the point-of-sale transaction may be stored utilizing a security processor in the WCD. The satellite positioning RF path may be powered down based on the determined location.

Abstract: Methods and systems for I/Q mismatch calibration and compensation for wideband communication receivers may include receiving a radio frequency (RF) signal in a receiver of a communication device, down-sampling the received RF signal to generate a channel k and its image channel ?k at baseband frequencies, and determining average in-phase (I) and quadrature (Q) gain and phase mismatch of the channel k and the image channel ?k. A curvature of gain mismatch for the channel k and the image channel ?k may be estimate utilizing a blind source separation (BSS) estimation algorithm. The average I and Q gain and phase mismatch of the channel k and the image channel ?k may be removed. A residual phase tilt and a residual amplitude tilt of the channel k and the image channel ?k (with removed average I and Q gain and phase mismatch) may be determined.

Abstract: Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Abstract: A method for authenticating and deciphering an encrypted program file for execution by a secure element includes receiving the program file and a digital certificate that is associated with the program file from an external device. The method stores the program file and the associated certificate in a secure random access memory disposed in the secure element and hashes the program file to obtain a hash. The method authenticates the program file by comparing the obtained hash with a checksum that is stored in the certificate. Additionally, the method writes runtime configuration information stored in the certificate to corresponding configuration registers disposed in the secure element. The method further generates an encryption key using a seed value stored in the certificate and a unique identifier disposed in the secure element and deciphers the program file using the generated encryption key.

Abstract: Methods and systems for femtocell positioning using low Earth orbit (LEO) satellite signals may comprise receiving LEO RF satellite signals utilizing a LEO satellite signal receiver path when medium Earth orbit (MEO) signals are attenuated below a threshold needed for positioning purposes by the MEO receiver path. A position of said wireless communication device (WCD) may be measured based on the received LEO RF satellite signals. The measured position of the WCD may be compared to a threshold radius defined by a stored initial position. Wireless communication services to the other WCDs may be enabled when the measured position is within the threshold radius. Reentry of the stored initial position may be requested when the measured position is outside of the threshold radius. The WCD may be disabled when the measured position of the WCD falls outside of the threshold radius more than a predetermined number of times.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.

Abstract: A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells.

Abstract: An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters allows frequencies higher than the frequency bandwidth of the desired signal, and a second of the two filters allows frequencies lower than the frequency bandwidth of the desired signal. The INMC may compute and store a mean magnitude separately for a first signal response of the first filter and a second signal response of the second filter. The INMC may select the first filter for impulse noise mitigation when the mean magnitude of the second filter is greater than the mean magnitude of the first filter. The INMC may select the second filter for impulse noise mitigation when the mean magnitude of the first filter is greater than the second filter.

Abstract: Methods and systems for impairment shifting may comprise receiving radio frequency (RF) signals in a receiver, downconverting the signals to baseband frequencies, and synchronizing the receiver to received signals. The frequency of a local oscillator (LO) may be adjusted to shift residual impairments to fall between desired baseband signals where they are least visible. The received RF signals may comprise analog, satellite, or cable, television signals. The LO frequency may be adjusted to configure the DC offset impairments to fall between luminance and chrominance harmonics. The LO frequency may be adjusted to configure I/Q imbalanced impairments from residual in-phase and quadrature mismatch of a picture carrier signal to fall about 300 kHz from a sound carrier signal in the analog television signals. The LO frequency may be adjusted to configure the I/Q imbalanced impairments from residual I/Q mismatch of a sound carrier signal to fall between luminance and chrominance harmonics.

Abstract: A signal receiver chip may be configured to handle a plurality of satellite signals. In this regard, for each received satellite signal the signal receiver chip may determine whether the received satellite signal is unprocessed or partially-processed off-chip; and when the received satellite signal is partially-processed off-chip, at least a portion of processing functions performed in the signal receiver chip may be bypassed. The received satellite signals may then be processed, to generate a corresponding output signals that is configured for communication over a local link. The processing functions bypassed in the signal receiver chip may comprise signal band conversion, particularly down converting from a first band used for over-the-air communication to a second band that is used during handling at receiver side. In this regard, the first band comprises K-band, Ku-band, or Ka-band, whereas the second band comprises L-band, half-L-band, or Extended-L-band.

Abstract: Methods and systems for a low input voltage low impedance termination stage for current inputs may include, in a semiconductor die, generating an output current proportional to an input signal, where the output current is generated by an output stage that may include a pair of input cascode transistors and at least one pair of stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor.

Abstract: Methods and systems for indoor global navigation satellite system detection utilizing low Earth orbit satellite signals may comprise receiving low Earth orbit (LEO) RF satellite signals utilizing a LEO satellite signal receiver path (LEO Rx) in a wireless communication device comprising the LEO satellite signal receiver path and a medium Earth orbit satellite signal receiver path (MEO Rx). A received signal strength indicator (RSSI) may be measured for the received LEO signals and an expected received MEO signal strength may be calculated. A power level of the MEO Rx may be configured based on the calculated MEO signal strength by powering down when the calculated expected MEO signal strength is below a threshold level for MEO positioning purposes and/or powered up when it increases above the threshold level. The RSSI may be measured at a plurality of points along the LEO Rx.

Abstract: An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit.

Abstract: Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

Abstract: Systems and methods are provided for implementing and using multiband transceiver architectures. In a transmit subsystem that comprises a plurality of transmit paths, a frequency spectrum that is used for transmission of signals may be segmented into a plurality of segments, and each of the segments may be allocated to one of the plurality of transmit paths. Further, performance in each of the plurality of transmit paths may be monitored during transmission of signals, and operation of the transmit subsystem and each of the plurality of transmit paths may be controlled based on the monitored performance. Such control may comprise dynamically performing one or more of modifying operation of one or more of the plurality of transmit paths, modifying assignment of plurality of segments to the plurality of transmit paths, and modifying segmentation of the frequency spectrum.

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: Methods and systems for providing satellite television service to a premises may comprise receiving satellite television signals utilizing a satellite dish, converting received satellite signals to internet protocol (IP) signals, and wirelessly communicating the IP signals into a premises to which the satellite dish corresponds. The IP signals may, for example, conform to a multimedia over cable alliance (MoCA) standard or a IEEE 802.11x standard. The wirelessly communicating may comprise magnetic coupling. The received satellite signals may, for example, be converted to IP signals utilizing an IP low-noise block downconverter (IP-LNB) which may comprise full-band capture receivers. The wireless communication of the IP signals may, for example, be within a wireless network of the dwelling or may be independent of a wireless network of the dwelling. The wirelessly communicated IP signals may be beam-formed and may be communicated wirelessly over one or more industrial, scientific, and medical (ISM) bands.

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: Methods and systems are provided for loop-through for multi-chip communication systems. Receiver circuitry, that is operable to receive one or more input feeds, may comprise a plurality of chips, each of which may be configurable to generate a corresponding output comprising one or more feed elements (e.g., channels) extracted from the input feed(s). However, only a first chip may be operable to handle reception and/or initial processing of the one or more input feeds, with each one of the remaining chips processing a loop-through feed generated by the first chip, in order to generate the corresponding output of that chip. The first chip generates the loop-through feed based on the one or more input feeds, such as after the initial processing thereof in the first chip. Generating the loop-through feed may comprise applying channelization (e.g., separately for each remaining chip), switching based processing, and/or interfacing based processing.