Abstract: Gas distribution units of fluidized bed reactors are configured to direct thermally decomposable compounds to the center portion of the reactor and away from the reactor wall to prevent deposition of material on the reactor wall and process for producing polycrystalline silicon product in a reactor that reduce the amount of silicon which deposits on the reactor wall.

Abstract: A support for a semiconductor wafer includes a plate having a support surface for supporting the wafer and a recessed surface spaced from the support surface and spaced from the wafer. A plurality of holes extends from the recessed surface, and the support surface is free of holes to inhibit contamination of the wafer.

Abstract: A wafer polishing apparatus has a base and a turntable having a polishing pad thereon and mounted on the base for rotation of the turntable and polishing pad relative to the base about an axis perpendicular to the turntable and polishing pad. The polishing pad includes a work surface engageable with a front surface of a wafer for polishing the front surface of the wafer. A drive mechanism is mounted on the base for imparting rotational motion about an axis substantially parallel to the axis of the turntable. A polishing head is connected to the drive mechanism for driving rotation of the polishing head. The polishing head has a pressure plate adapted to hold the wafer for engaging the front surface of the wafer with the work surface of the polishing pad. The pressure plate has a generally planar position and is selectively movable from the planar position to a convex position and to a concave position.

Abstract: This invention is directed to a process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having the desired vacancy concentration profile. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: System for controlling crystal growth in a Czochralski crystal growing apparatus. A magnetic field is applied within the crystal growing apparatus and varied to control a shape of the melt-solid interface where the ingot is being pulled from the melt. The shape of the melt-solid interface is formed to a desired shape in response to the varied magnetic field as a function of a length of the ingot.

Abstract: A feed assembly and method of use thereof of the present invention is used for the addition of a high pressure dopant such as arsenic into a silicon melt for CZ growth of semiconductor silicon crystals. The feed assembly includes a vessel-and-valve assembly for holding dopant, and a feed tube assembly, attached to the vessel-and-valve assembly for delivering dopant to a silicon melt. An actuator is connected to the feed tube assembly and a receiving tube for advancing and retracting the feed tube assembly to and from the surface of the silicon melt. A brake assembly is attached to the actuator and the receiving tube for restricting movement of the feed tube assembly and locking the feed tube assembly at a selected position.

Abstract: A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.

Abstract: This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.

Abstract: A wiresaw beam for use in an apparatus for slicing wafers from an ingot, such as semiconductor wafers from a single crystal ingot or a polycrystalline silicon ingot. The wiresaw beam may be made from a polymer composite material comprising a thermoset polymer resin and carbon nanotubes.

Abstract: A method of continuously measuring an elevation and shape of an unmelted polycrystalline silicon island during a silicon meltdown process. The method comprises projecting a focused bright light on the silicon island to produce a bright dot on the silicon island. The method also includes electronically determining an elevation and a shape of the silicon island by tracking the bright dot during the meltdown process.

Abstract: A silicon structure with improved protection against failures induced by excess radiation-induced charge carrier migration from the bulk region into the near-surface region. The structure comprises bulk and near-surface regions that are doped with a dopant, wherein the concentration in the near-surface region is at least 10 times the maximum concentration, c, of dopant in the bulk region. The structure further comprises a transition region between the bulk and near-surface regions extending less than about 1 ?m from the near-surface region toward the central plane.

Abstract: Semiconductor wafers have a front surface, a back surface, a notch, and an edge. A method of polishing a wafer includes polishing at least one of the surfaces and the notch of the wafer using a polishing pad and slurry. At least one surface of the wafer is cleaned of residual slurry. The cleaned surface is grasped by applying a vacuum to the cleaned surface of the wafer using a vacuum chuck. Edge of the wafer is polished using a pad and slurry while the wafer is grasped by the vacuum chuck.

Abstract: A system for polishing a semiconductor wafer. The system includes a polishing apparatus having a rotatable polishing pad for polishing the wafer. A dressing apparatus is mounted adjacent the polishing pad for dressing the polishing pad. The dressing apparatus includes a dressing member engageable with the polishing pad. A cleaning apparatus is mounted adjacent the polishing pad for removing particulate and chemicals from the polishing pad. The system includes a controller for controlling the dressing apparatus and the cleaning apparatus.

Abstract: A susceptor for supporting a semiconductor wafer during a chemical vapor deposition process includes a body having opposing upper and lower surfaces. Support bosses extend downward from the lower face of the body. Each support boss has a boss opening sized and shaped for receiving a support post of a chemical vapor deposition device to mount the susceptor on the support post.

Abstract: A carrier blade for transferring a semiconductor wafers into and out of a deposition chamber may include transition surfaces sloping downward from ledge surfaces. The transition surfaces slope from the corresponding ledges at angles that are greater than about 90 degrees so that the edges between the ledge surfaces and the transition surfaces are not sharp. The carrier blade may include bevels extending from the ledge surface(s) to upper lateral edges of the carrier blade.

Abstract: A barrel susceptor for supporting semiconductor wafers in a heated chamber having an interior space. Each of the wafers has a front surface, a back surface and a circumferential side. The susceptor includes a body having a plurality of faces arranged around an imaginary central axis of the body. Each face has an outer surface and a recess extending laterally inward into the body from the outer surface. Each recess is surrounded by a rim defining the respective recess. The susceptor also includes a plurality of ledges extending outward from the body. Each of the ledges is positioned in one of the recesses and includes an upward facing support surface for supporting a semiconductor wafer received in the recess. Each of the support surfaces is separate from the outer surface of the respective face.