Abstract: A barrel susceptor for supporting semiconductor wafers in a heated chamber having an interior space. Each of the wafers has a front surface, a back surface and a circumferential side. The susceptor includes a body having a plurality of faces arranged around an imaginary central axis of the body. Each face has an outer surface and a recess extending laterally inward into the body from the outer surface. Each recess is surrounded by a rim defining the respective recess. The susceptor also includes a plurality of ledges extending outward from the body. Each of the ledges is positioned in one of the recesses and includes an upward facing support surface for supporting a semiconductor wafer received in the recess. Each of the support surfaces is separate from the outer surface of the respective face.
Type:
Application
Filed:
December 27, 2007
Publication date:
July 2, 2009
Applicant:
MEMC ELECTRONIC MATERIALS, INC.
Inventors:
Lance G. Hellwig, Srikanth Kommu, John A. Pitney
Abstract: A susceptor for supporting a semiconductor wafer during a chemical vapor deposition process includes a body having opposing upper and lower surfaces. Support bosses extend downward from the lower face of the body. Each support boss has a boss opening sized and shaped for receiving a support post of a chemical vapor deposition device to mount the susceptor on the support post.
Type:
Application
Filed:
December 27, 2007
Publication date:
July 2, 2009
Applicant:
MEMC ELECTRONIC MATERIALS, INC.
Inventors:
John A. Pitney, Manabu Hamano, Lance G. Hellwig
Abstract: A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
Type:
Application
Filed:
December 31, 2008
Publication date:
May 21, 2009
Applicant:
MEMC ELECTRONIC MATERIALS, INC.
Inventors:
Robert J. Falster, Vladimir V. Voronkov, Gabriella Borionetti
Abstract: A process is provided for controlling the amount of insoluble gas carried by a charge of granular polycrystalline silicon. The process comprises (i) charging a feeding container with granular polycrystalline silicon, (ii) forming an ambient atmosphere in the feeding container, the ambient atmosphere having a mole fraction of at least 0.9 of a gas having a solubility in molten silicon of at least about 5—1013 atoms/cm3 at a temperature near the melting point of silicon and at a pressure of about 1 bar (about 100 kPa), and (iii) reducing the pressure inside the charged feeding container.
Abstract: The present invention generally relates to a high resistivity CZ silicon wafer, or a high resistivity silicon structure derived therefrom, and a process for the preparation thereof. In particular, the high resistivity silicon structure comprises a large diameter CZ silicon wafer as the substrate thereof, wherein the resistivity of the substrate wafer is decoupled from the concentration of acceptor atoms (e.g., boron) therein, the resistivity of the substrate being substantially greater than the resistivity as calculated based on the concentration of said acceptor atoms therein.
Type:
Grant
Filed:
May 18, 2006
Date of Patent:
April 21, 2009
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Robert J. Falster, Vladimir V. Voronkov, Galina I. Voronkova, Anna V. Batunina
Abstract: Processes for purifying silicon tetrafluoride source gas by subjecting the source gas to one or more purification processes including: contacting the silicon tetrafluoride source gas with an ion exchange resin to remove acidic contaminants, contacting the silicon tetrafluoride source gas with a catalyst to remove carbon monoxide, by removal of carbon dioxide by use of an absorption liquid, and by removal of inert compounds by cryogenic distillation; catalysts suitable for removal of carbon monoxide from silicon tetrafluoride source gas and processes for producing such catalysts.
Abstract: The present invention is directed to a method for treatment of a gas stream comprising silicon tetrafluoride and hydrogen chloride. For example, the present invention is directed to a method for treatment of such a gas stream that involves contacting the gas stream with a metal that reacts with the hydrogen chloride to provide a treated gas stream having reduced hydrogen chloride content. The present invention is further directed to methods for subjecting silicon tetrafluoride and hydrogen chloride-containing gas streams to elevated pressure to provide gas streams suitable for transport.
Abstract: A vitreous crucible for holding semiconductor material during a moncrystalline ingot growing process has a sidewall. Part of the sidewall is coated with a devitrification promoter and part of the sidewall is substantially free from devitrification promoter coating. When the crucible is heated as it would be during an ingot growing process, the devitrification promoter induces crystallization of portions of the sidewall, thereby forming enhanced stiffness sidewall portions. Areas that are substantially free from devitrification promoters remain vitreous and are softened by the heat. These become stress accommodating sidewall portions. Flow of the vitreous material in the stress accommodating sidewall portions relieves stresses that would otherwise build up in the sidewall.
Abstract: A process for the preparation of low resistivity arsensic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
Type:
Grant
Filed:
November 9, 2005
Date of Patent:
February 3, 2009
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Robert J. Falster, Vladimir Voronkov, Gabriella Borionetti
Abstract: A process for producing a single crystal silicon wafer comprising a front surface, a back surface, a lateral surface joining the front and back surfaces, a central+ axis perpendicular to the front and back surfaces, and a segment which is axially symmetric about the central axis extending substantially from the front surface to the back surface in which crystal lattice vacancies are the predominant intrinsic point defect, the segment having a radial width of at least about 25% of the radius and containing agglomerated vacancy defects and a residual concentration of crystal lattice vacancies wherein (i) the agglomerated vacancy defects have a radius of less than about 70 nm and (ii) the residual concentration of crystal lattice vacancy intrinsic point defects is less than the threshold concentration at which uncontrolled oxygen precipitation occurs upon subjecting the wafer to an oxygen precipitation heat treatment.
Type:
Application
Filed:
October 2, 2008
Publication date:
January 22, 2009
Applicant:
MEMC ELECTRONIC MATERIALS, INC.
Inventors:
Robert J. Falster, Vladimir V. Voronkov, Paolo Mutti, Francesco Bonoli
Abstract: This invention generally relates to a process for suppressing oxygen precipitation in epitaxial silicon wafers having a heavily doped silicon substrate and a lightly N-doped silicon epitaxial layer by dissolving existing oxygen clusters and precipitates within the substrate. Furthermore, the formation of oxygen precipitates is prevented upon subsequent oxygen precipitation heat treatment.
Type:
Application
Filed:
June 29, 2007
Publication date:
January 1, 2009
Applicant:
MEMC Electronic Materials, Inc.
Inventors:
Robert J. Falster, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani
Abstract: This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.
Type:
Application
Filed:
June 29, 2007
Publication date:
January 1, 2009
Applicant:
MEMC Electronic Materials, Inc.
Inventors:
Robert J. Falster, Vladimir V. Voronkov, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani
Abstract: A susceptor for supporting a semiconductor wafer in a heated chamber having an interior space. The susceptor includes a body having an upper surface and a lower surface opposite the upper surface. The susceptor also has a recess extending downward from the upper surface into the body along an imaginary central axis. The recess is sized and shaped for receiving the semiconductor wafer therein. The susceptor includes a plurality of lift pin openings extending through the body from the recess to the lower surface. Each of the lift pin openings is sized for accepting lift pins to selectively lift and lower the wafer with respect to the recess. The susceptor has a central opening extending through the body along the central axis from the recess to the lower surface.
Type:
Application
Filed:
December 27, 2007
Publication date:
December 25, 2008
Applicant:
MEMC ELECTRONIC MATERIALS, INC.
Inventors:
Manabu Hamano, Srikanth Kommu, John A. Pitney, Thomas A. Torack, Lance G. Hellwig
Abstract: The invention concerns a process (and a corresponding plant) for the purification of trichlorosilane and/or silicon tetrachloride comprising the following steps of treating technical grade trichlorosilane and/or technical grade silicon tetrachloride: complexation of the boron impurities (trichloride BCI3) and other metallic impurities by addition of diphenylthiocarbazone and/or triphenylchloromethane, with the formation of complex macromolecules having high boiling point, first column distillation of the complexation step products, wherein the complexed boron impurities, together with other metallic impurities are removed as bottoms, and second column distillation of the tops of the previous distillation, wherein electronic grade trichlorosilane (plus dichlorosilane possible present) and/or silicon tetrachloride are obtained as tops and phosphorus chlorides PCI3 and phosphorus containing compounds, arsenic chlorides AsCI3 and arsenic containing compounds, aluminium compounds, antimony compounds and in general
Abstract: A method of servicing multiple crystal forming apparatus with a single melter assembly is provided. The method includes the steps of positioning the melter assembly relative to a first crystal forming apparatus for delivering molten silicon to a crucible of the first apparatus. A heater in the melter assembly is operated to melt source material in a melting crucible. A stream of molten source material is delivered from the melter assembly to the first crystal forming apparatus. The melter assembly is positioned relative to a second crystal forming apparatus for delivering molten silicon to a crucible of the second apparatus. A stream of molten source material is transferred from the melter assembly to the second crystal forming apparatus.
Abstract: A susceptor for supporting wafers during an chemical vapor deposition process. The susceptor has recesses and orifices disposed in the recesses extending to a central passage of the susceptor. The susceptor has exhaust openings disposed in the top of the susceptor to allow gas from the central passage of the susceptor to exit out the openings. A baffle plate covers the exhaust openings and a vertical space is created between the baffle plate and the top of the susceptor to allow gas to exit from the central passage to outside the susceptor. The bottom of the susceptor also has exhaust openings disposed therein. These openings allow gas from the central passage to exit the susceptor.
Abstract: The present invention is directed to a process for producing a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects. The process either comprises exposing the wafer's front and back surfaces to different atmospheres, or thermally annealing two wafers in a face-to-face arrangement.
Type:
Grant
Filed:
May 24, 2007
Date of Patent:
October 28, 2008
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Robert J. Falster, Joseph C. Holzer, Marco Cornara, Daniela Gambaro, Massimiliano Olmo, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
Abstract: A process for producing a single crystal silicon wafer comprising a front surface, a back surface, a lateral surface joining the front and back surfaces, a central axis perpendicular to the front and back surfaces, and a segment which is axially symmetric about the central axis extending substantially from the front surface to the back surface in which crystal lattice vacancies are the predominant intrinsic point defect, the segment having a radial width of at least about 25% of the radius and containing agglomerated vacancy defects and a residual concentration of crystal lattice vacancies wherein (i) the agglomerated vacancy defects have a radius of less than about 70 nm and (ii) the residual concentration of crystal lattice vacancy intrinsic point defects is less than the threshold concentration at which uncontrolled oxygen precipitation occurs upon subjecting the wafer to an oxygen precipitation heat treatment.
Type:
Grant
Filed:
March 24, 2005
Date of Patent:
October 7, 2008
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Robert J. Falster, Vladimir V. Voronkov, Paolo Mutti, Francesco Bonoli
Abstract: A high-purity semiconductor grade granular silicon composition, which can be produced in commercial quantities, is disclosed. In one embodiment the composition comprises a plurality of free-flowing particles having a total weight of at least about 300 kg and an average transition metal concentration of less than 0.2 ppba. In another embodiment the composition comprises a plurality of free-flowing silicon particles having a total weight of at least about 300 kg and at least 99 percent of the particles are between about 250 and 3500 microns in size.
Abstract: The present invention relates to a process for forming single crystal silicon ingots or wafers that contain an axially symmetric region in which vacancies are the predominant intrinsic point defect, that are substantially free of oxidation induced stacking faults, and are nitrogen doped to stabilize oxygen precipitation nuclei therein.