Patents Assigned to MEMC
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Publication number: 20050238905Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, having an axially symmetric vacancy dominated region and an axially symmetric silicon self-interstitial dominated region. Both the vacancy dominated and the silicon self-interstitial dominated regions are substantially free of agglomerated intrinsic point defects. The vacancy dominated region has a radial width of at least 15 mm and/or includes the central axis and the silicon self-interstitial dominated region is annular in shape and extends radially outward from the vacancy dominated region to the peripheral edge of the ingot or wafer. In ingot form, the axially symmetric regions have an axial length which is at least 20% of the length of the constant diameter portion of the ingot.Type: ApplicationFiled: April 8, 2005Publication date: October 27, 2005Applicant: MEMC Electronic Materials, Inc.Inventors: Robert Falster, Joseph Holzer, Steve Markgraf, Paolo Mutti, Seamus McQuaid, Bayard Johnson
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Patent number: 6958092Abstract: A wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer. In addition, the front surface of the wafer has an epitaxial layer, having a thickness of less than about 2.0 çm, deposited thereon. A process comprises heating a surface of a wafer starting material to remove a silicon oxide layer from the surface and depositing an epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant, and the wafer is cooled at a rate of at least about 10C./sec.Type: GrantFiled: March 25, 2003Date of Patent: October 25, 2005Assignee: MEMC Electronic Materials, Inc.Inventors: Gregory M. Wilson, Jon A. Rossi, Charles C. Yang
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Patent number: 6955718Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has a non-uniform distribution of stabilized oxygen precipitate nucleation centers therein. Specifically, the peak concentration is located in the wafer bulk and a precipitate-free zone extends inward from a surface.Type: GrantFiled: July 8, 2003Date of Patent: October 18, 2005Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Vladimir V. Voronkov
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Publication number: 20050205000Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process comprises controlling growth conditions, such as growth velocity, v, instantaneous axial temperature gradient, G0, and the cooling rate, within a range of temperatures at which silicon self-interstitials are mobile, in order to prevent the formation of these agglomerated defects. In ingot form, the axially symmetric region has a width, as measured from the circumferential edge of the ingot radially toward the central axis, which is at least about 30% the length of the radius of the ingot. The axially symmetric region additionally has a length, as measured along the central axis, which is at least about 20% the length of the constant diameter portion of the ingot.Type: ApplicationFiled: May 17, 2005Publication date: September 22, 2005Applicant: MEMC Electronic Materials, Inc.Inventors: Robert Falster, Joseph Holzer
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Patent number: 6941940Abstract: A wire saw (10) for simultaneously slicing multiple, generally cylindrical monocrystalline ingots (14) into wafers. The wire saw includes a cutting head (16), an ingot support (12), and multiple generally parallel lengths of cutting wire (18) defining a cutting web (30). A slurry delivery system includes nozzles (34, 36, and 38) positioned for dispensing slurry along the wire web generally at lateral sides of each ingot. A process for simultaneously slicing at least two generally cylindrical semiconductor ingots into wafers includes mounting at least two ingots to a common ingot support, moving the ingot support relative to the cutting web so that the two ingots simultaneously press against the cutting web at cutting regions, and dispensing a liquid slurry to at least three locations on the wire web including two outermost sides of the cutting regions and a location between each pair of ingots.Type: GrantFiled: May 31, 2000Date of Patent: September 13, 2005Assignee: MEMC Electronic Materials, S.p.A.Inventors: Carlo Zavattari, Ferdinando Severico, Paolo De Maria
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Patent number: 6942733Abstract: A fluid sealing system is provided for use in a crystal puller for growing a monocrystalline ingot. The crystal puller has a housing, a fluid flow path contained in the housing, and a fluid passage through a wall of the housing for passage of fluid. The fluid sealing system includes a fluid connector head adapted for connection to the fluid passage and to the fluid flow path to establish fluid communication between the fluid flow path and the outside of the housing. The head has a port adapted for fluid communication with the fluid passage through the wall of the housing. First and second seals around the port are adapted for sealing engagement with the head. A space is defined generally between the first and second seals, and a leak detector is arranged to monitor the space for detecting fluid leakage past at least one of the seals.Type: GrantFiled: June 19, 2003Date of Patent: September 13, 2005Assignee: MEMC Electronics Materials, Inc.Inventors: Carl F. Cherko, Robert D. Cook
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Patent number: 6930375Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.Type: GrantFiled: June 21, 2002Date of Patent: August 16, 2005Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Jeffrey L. Libbert
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Publication number: 20050170610Abstract: The present invention is directed to a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects.Type: ApplicationFiled: February 16, 2005Publication date: August 4, 2005Applicant: MEMC Electronic Materials, Inc.Inventors: Robert Falster, Joseph Holzer, Marco Cornara, Daniela Gambaro, Massimiliano Olmo, Steve Markgraf, Paolo Mutti, Seamus McQuaid, Bayard Johnson
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Publication number: 20050160967Abstract: A process for producing a single crystal silicon wafer comprising a front surface, a back surface, a lateral surface joining the front and back surfaces, a central axis perpendicular to the front and back surfaces, and a segment which is axially symmetric about the central axis extending substantially from the front surface to the back surface in which crystal lattice vacancies are the predominant intrinsic point defect, the segment having a radial width of at least about 25% of the radius and containing agglomerated vacancy defects and a residual concentration of crystal lattice vacancies wherein (i) the agglomerated vacancy defects have a radius of less than about 70 nm and (ii) the residual concentration of crystal lattice vacancy intrinsic point defects is less than the threshold concentration at which uncontrolled oxygen precipitation occurs upon subjecting the wafer to an oxygen precipitation heat treatment.Type: ApplicationFiled: March 24, 2005Publication date: July 28, 2005Applicant: MEMC Electronic Materials, Inc.Inventors: Robert Falster, Vladimir Voronkov, Paolo Mutti, Francesco Bonoli
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Publication number: 20050158969Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.Type: ApplicationFiled: March 17, 2005Publication date: July 21, 2005Applicant: MEMC Electronic Materials, Inc.Inventors: Martin Binns, Robert Falster, Jeffrey Libbert
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Publication number: 20050150445Abstract: The present invention relates to a process for preparing a single crystal silicon ingot, as well as to the ingot or wafer resulting therefrom. The process comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, and (iii) a cooling rate of the crystal from solidification to about 750° C., in order to cause the formation of a segment having a first axially symmetric region extending radially inward from the lateral surface of the ingot wherein silicon self-interstitials are the predominant intrinsic point defect, and a second axially symmetric region extending radially inward from the first and toward the central axis of the ingot.Type: ApplicationFiled: December 7, 2004Publication date: July 14, 2005Applicant: MEMC Electronic Materials, Inc.Inventors: Chang Kim, Steven Kimbel, Jeffrey Libbert, Mohsen Banan
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Process for cooling a silicon ingot having a vacancy dominated region to produce defect free silicon
Patent number: 6913647Abstract: A process for producing silicon which is substantially free of agglomerated intrinsic point defects in an ingot having a vacancy dominated region. An ingot is grown generally in accordance with the Czochralski method. While intrinsic point defects diffuse from or are annihilated within the ingot, at least a portion of the ingot is maintained above a temperature TA at which intrinsic point defects agglomerate. The achievement of defect free silicon is thus substantially decoupled from process parameters, such as pull rate, and system parameters, such as axial temperature gradient in the ingot.Type: GrantFiled: May 13, 2003Date of Patent: July 5, 2005Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Harold W. Korb -
Publication number: 20050132948Abstract: A process for the preparation of a silicon single ingot in accordance with the Czochralski method. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C. to initially produce in the constant diameter portion of the ingot a series of predominant intrinsic point defects including vacancy dominated regions and silicon self interstitial dominated regions, alternating along the axis, and cooling the regions from the temperature of solidification at a rate which allows silicon self-interstitial atoms to diffuse radially to the lateral surface and to diffuse axially to vacancy dominated regions to reduce the concentration intrinsic point defects in each region.Type: ApplicationFiled: February 16, 2005Publication date: June 23, 2005Applicant: MEMC Electronic Materials, Inc.Inventors: Vladimir Vornokov, Robert Falster, Mohsen Banan
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Patent number: 6897084Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.Type: GrantFiled: April 11, 2002Date of Patent: May 24, 2005Assignee: MEMC Electronic Materials, Inc.Inventors: Martin Jeffrey Binns, Robert J. Falster, Jeffrey L. Libbert
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Patent number: 6896728Abstract: The present invention is directed to a process for producing a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects. The process including growing a single crystal silicon ingot from molten silicon, and as part of the growth process, controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C., and (iii) a cooling rate of the crystal from a solidification temperature to about 1,050° C., in order to cause the formation of an axially symmetrical segment which is substantially free of agglomerated intrinsic point defects.Type: GrantFiled: February 25, 2003Date of Patent: May 24, 2005Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Joseph C. Holzer, Marco Cornara, Daniela Gambaro, Massimiliano Olmo, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
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Patent number: 6878302Abstract: The method comprises the steps of mounting a first wafer (13) on the mounting member (12) and securing the mounting member to the hub (16) by drawing a vacuum at a first vacuum pressure through the hub; rotating the hub about the hub axis (AH), rotating a polishing pad (34) mounted on the turntable (30) about the turntable axis (at), and bringing a surface of the wafer (13) and the polishing pad into contact with each other. The wafer (16) is demounted, and the shape of the polished wafer is determined. A second vacuum pressure is selected using the information obtained. A successive wafer is polished according to the same method as the first wafer except that the second vacuum pressure is substituted for the first vacuum pressure. The second vacuum pressure is sufficient to deform the mounting member (12) thereby deform the wafer to improve the flatness and parallelism of the surfaces of the successive wafer.Type: GrantFiled: March 30, 2000Date of Patent: April 12, 2005Assignee: MEMC Electronic Materials, SpAInventors: Paride Corbellini, Giovanni Negri, Ezio Bovio, Luca Moiraghi
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Patent number: 6869477Abstract: A process for preparing a single crystal silicon in accordance with the Czochralski method, is provided. More specifically, by quickly reducing the pull rate at least once during the growth of the neck portion of the single crystal ingot, in order to change the melt/solid interface shape from a concave to a convex shape, the present process enables zero dislocation growth to be achieved in a large diameter neck within a comparably short neck length, such that large diameter ingots of substantial weight can be produced safely and at a high throughput.Type: GrantFiled: February 20, 2001Date of Patent: March 22, 2005Assignee: MEMC Electronic Materials, Inc.Inventors: Hiroyo Haga, Makoto Kojima, Shigemi Saga
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Patent number: 6866713Abstract: The present invention provides for a process for preparing a single crystal silicon ingot by the Czochralski method. The process comprises selecting a seed crystal for Czochralski growth wherein the seed crystal comprises vacancy dominated single crystal silicon.Type: GrantFiled: October 28, 2002Date of Patent: March 15, 2005Assignee: MEMC Electronic Materials, Inc.Inventors: Hariprasad Sreedharamurthy, Mohsen Banan
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Patent number: 6858307Abstract: A process for the preparation of a silicon single ingot in accordance with the Czochralski method. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C. to initially produce in the constant diameter portion of the ingot a series of predominant intrinsic point defects including vacancy dominated regions and silicon self interstitial dominated regions, alternating along the axis, and cooling the regions from the temperature of solidification at a rate which allows silicon self-interstitial atoms to diffuse radially to the lateral surface and to diffuse axially to vacancy dominated regions to reduce the concentration intrinsic point defects in each region.Type: GrantFiled: October 5, 2001Date of Patent: February 22, 2005Assignee: MEMC Electronic Materials, Inc.Inventors: Vladimir V. Vornokov, Robert J. Falster, Mohsen Banan
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Patent number: 6849901Abstract: The present invention relates to a process for the preparation of a silicon on insulator wafer. The process includes implanting oxygen into a single crystal silicon wafer which is substantially free of agglomerated vacancy-type defects. The present invention further relates to a process for the preparation of a silicon on insulator wafer wherein oxygen is implanted into a single crystal silicon wafer having an axially symmetric region in which there is a predominant intrinsic point defect which is substantially free of agglomerated intrinsic point defects. Additionally, the present invention relates to a silicon on insulator (“SOI”) structure in which the device layer and the handle wafer each have an axially symmetric region which is substantially free of agglomerated intrinsic point defects.Type: GrantFiled: January 3, 2002Date of Patent: February 1, 2005Assignee: MEMC Electronic Materials, Inc.Inventor: Robert J. Falster