Abstract: A susceptor for supporting wafers during an chemical vapor deposition process. The susceptor has recesses and orifices disposed in the recesses extending to a central passage of the susceptor. The susceptor has exhaust openings disposed in the top of the susceptor to allow gas from the central passage of the susceptor to exit out the openings. A baffle plate covers the exhaust openings and a vertical space is created between the baffle plate and the top of the susceptor to allow gas to exit from the central passage to outside the susceptor. The bottom of the susceptor also has exhaust openings disposed therein. These openings allow gas from the central passage to exit the susceptor.

Abstract: A process for the preparation of a silicon single ingot in accordance with the Czochralski method. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C. to initially produce in the constant diameter portion of the ingot a series of predominant intrinsic point defects including vacancy dominated regions and silicon self interstitial dominated regions, alternating along the axis, and cooling the regions from the temperature of solidification at a rate which allows silicon self-interstitial atoms to diffuse radially to the lateral surface and to diffuse axially to vacancy dominated regions to reduce the concentration intrinsic point defects in each region.

Abstract: Epitaxial wafers comprising a single crystal silicon substrate comprising agglomerated vacancy defects and having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated intrinsic point defects on the substrate surface upon which the epitaxial layer is deposited.

Abstract: A process for removing a contaminant selected from among copper, nickel, and a combination thereof from a silicon wafer having a surface and an interior. The process comprises cooling the silicon wafer in a controlled atmosphere from a temperature at or above an oxidation initiation temperature and initiating a flow of an oxygen-containing atmosphere at said oxidation initiation temperature to create an oxidizing ambient around the silicon wafer surface to form an oxide layer on the silicon wafer surface and a strain layer at an interface between the oxide layer and the silicon wafer interior. The cooling of the wafer is also controlled to permit diffusion of atoms of the contaminant from the silicon wafer interior to the strain layer. Then the silicon wafer is then cleaned to remove the oxide layer and the strain layer, thereby removing said contaminant having diffused to the strain layer.

Abstract: A method and system for use in combination with a crystal growing apparatus for growing a monocrystalline ingot according to a Czochralski process. The crystal growing apparatus has a heated crucible including a semiconductor melt from which the ingot is pulled. The ingot is grown on a seed crystal pulled from the melt. A time varying external magnetic field is imposed on the melt during pulling of the ingot. The magnetic field is selectively adjusted to produce pumping forces in the melt to control a melt flow velocity while the ingot is being pulled from the melt.

Abstract: Methods and system for controlling crystal growth in a Czochralski crystal growing apparatus. A magnetic field is applied within the crystal growing apparatus and varied to control a shape of the melt-solid interface where the ingot is being pulled from the melt. The shape of the melt-solid interface is formed to a desired shape in response to the varied magnetic field as a function of a length of the ingot.

Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Abstract: A heteroepitaxial semiconductor wafer includes a heteroepitaxial layer forming the front surface of the wafer that includes a secondary material having a different crystal structure than that of the wafer primary material. The heteroepitaxial layer is substantially free of defects. A surface layer includes the primary material and is free of the secondary material. The surface layer borders the heteroepitaxial layer. A bulk layer includes the primary material and is free of the secondary material. The bulk layer borders the surface layer and extends through the central plane. An SOI wafer and a method of making wafers is disclosed.

Abstract: A high-purity semiconductor grade granular silicon composition and methods for making the same are disclosed. Commercial quantities of the granular silicon can be produced by depositing silicon on silicon seeds in a first chemical vapor deposition (CVD)reactor, thereby growing the seeds into larger secondary seeds. Additional silicon is deposited on the secondary seeds in a second CVD reactor. Dust is reduced in a third reactor. The methods disclosed herein can be used to achieve higher throughput and better yield than conventional practices.

Abstract: A wafer boat for use in heat treatment of semiconductor wafers in a vertical furnace comprises support rods extending generally vertically when the wafer boat is placed in the vertical furnace. Fingers are supported by and extend along vertical extent of the support rods. Wafer holder platforms are adapted to be supported by groups of fingers lying in generally different common horizontal planes. The fingers are adapted to underlie the wafer holder platforms and support the platforms at the support locations. The fingers and wafer holder platforms each have a respective first overall maximum thickness. The support location of at least one of the fingers and the wafer holder platforms have a second maximum thickness less than the first overall maximum thickness.

Abstract: A process for nucleating and growing oxygen precipitates in a silicon wafer, including subjecting a wafer having a non-uniform concentration of crystal lattice vacancies with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer to a non-isothermal heat treatment to form of a denuded zone in the surface layer and to cause the formation and stabilization of oxygen precipitates having an effective radial size 0.5 nm to 30 nm in the bulk layer. The process optionally includes subjecting the stabilized wafer to a high temperature thermal process (e.g. epitaxial deposition, rapid thermal oxidation, rapid thermal nitridation and etc.) at temperatures in the range of 1000 OC to 1275 OC without causing the dissolution of the stabilized oxygen precipitates.

Abstract: The present invention is directed to a process for reclaiming for reuse a single crystal silicon wafer removed from an aborted semiconductor device fabrication process. The process includes (a) subjecting the wafer to an oxide growth step to form an oxide layer having a thickness greater than 2 nanometers, (b) thinning the wafer by removing material from substantially the entire front surface to provide a thinned wafer having a thinned precipitate free zone, and (c) polishing the front surface of the thinned wafer to a specular finish.

Abstract: A wafer carrier for retaining at least one semiconductor wafer in a processing apparatus during a processing operation which removes wafer material by at least one of abrading and chemical reaction. The processing apparatus is adapted for removing wafer material from a front side and a back side of each wafer simultaneously. The carrier includes a plate including wafer contaminating material and having an opening and a thickness. An insert has a thickness and is disposed in the opening for receiving at least one wafer and engaging a peripheral edge of the wafer to hold the wafer as the carrier rotates. The thickness of the insert is significantly greater than the thickness of the plate to inhibit removal of material from the plate and thereby inhibit bulk metal contamination of the wafer.

Abstract: A single crystal silicon wafer comprising a front surface, a back surface, a lateral surface joining the front and back surfaces, a central axis perpendicular to the front and back surfaces, and a segment which is axially symmetric about the central axis extending substantially from the front surface to the back surface in which crystal lattice vacancies are the predominant intrinsic point defect, the segment having a radial width of at least about 25% of the radius and containing agglomerated vacancy defects and a residual concentration of crystal lattice vacancies wherein (i) the agglomerated vacancy defects have a radius of less than about 70 nm and (ii) the residual concentration of crystal lattice vacancy intrinsic point defects is less than the threshold concentration at which uncontrolled oxygen precipitation occurs upon subjecting the wafer to an oxygen precipitation heat treatment.

Abstract: The present invention provides a methods and system for producing semiconductor grade single crystals that are substantially free of undesirable agglomerated defects. A vacancy/interstial (V/I) boundary simulator analyzes various melt-solid interface shapes to predict a corresponding V/I transition curve for each of the various melt-solid interface shapes. A target melt-solid interface shape corresponding to a substantially flat V/I curve is identified for each of a plurality of axial positions along the length of the crystal. Target operating parameters to achieve each of the identified melt-solid interface shapes are stored in a melt-solid interfaced shape profile. A control system is responsive to the stored profile to generate one or more control signals to control one or more output devices such that the melt-solid interfaced shape substantially follows the target shapes as defined by the profile during crystal growth.

Abstract: A method of charging a crystal forming apparatus with molten source material is provided. The method includes the steps of positioning a melter assembly relative to the crystal forming apparatus for delivering molten silicon to a crucible of the apparatus. An upper heating coil in the melter assembly is operated to melt source material in a melting crucible. A lower heating coil in the melter assembly is operated to allow molten source material to flow through an orifice of the melter assembly to deliver a stream of molten source material to the crucible of the crystal forming apparatus. The invention is also directed to a method of charging a crystal puller with molten silicon including the step of removing an upper housing of the crystal puller defining a pulling chamber from a lower housing of the crystal puller defining a growth chamber and attaching the lower housing in place of the upper housing.

Abstract: A method of servicing multiple crystal forming apparatus with a single melter assembly is provided. The method includes the steps of positioning the melter assembly relative to a first crystal forming apparatus for delivering molten silicon to a crucible of the first apparatus. A heater in the melter assembly is operated to melt source material in a melting crucible. A stream of molten source material is delivered from the melter assembly to the first crystal forming apparatus. The melter assembly is positioned relative to a second crystal forming apparatus for delivering molten silicon to a crucible of the second apparatus. A stream of molten source material is transferred from the melter assembly to the second crystal forming apparatus.

Abstract: A melter assembly supplies a charge of molten source material to a crystal forming apparatus for use in forming crystalline bodies. The melter assembly comprises a housing and a crucible located in the housing. A heater is disposed relative to the crucible for melting solid source material received in the crucible. The crucible has a nozzle to control the flow of molten source material such that a directed flow of molten source material can be supplied to the crystal forming apparatus at a selected flow rate.

Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Abstract: A method and apparatus for controlling the quenching rate of a monocrystalline ingot pulled from a melt by adjusting one or more post growth processing parameter. A temperature model generates a temperature profile that represents the surface temperature along the length of the ingot at the instant it is pulled from the melt. A first temperature at a particular location along the length of the crystal is determined from the temperature profile. A temperature sensor senses a second temperature at the same particular location. A PLC calculates a quenching rate of the crystal as a function of the first temperature and the second temperature. The PLC generates an error between a target quenching rate and a calculated quenching rate, and one or more post growth process parameters are adjusted as function of the error signal to optimize the quenching rate.