Patents Assigned to MEMC
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Patent number: 6515742Abstract: A system and method for detecting and classifying defects associated with the surface of semiconductor wafers, namely silicon wafers. An inspection device directs a laser light onto the wafer surface. Defects on the surface scatter the laser light into a plurality of photomultiplier tubes positioned to collect light scattered in distinct and separate collection angles. The photomultiplier tubes generate signals indicative of the estimated size of a defect causing the light to scatter based on the intensity of the light received by each respective photomultiplier tube. A processor compares the size estimations to a plurality of empirically determined power functions to identify the most likely type of the defect. The empirically determined power functions are derived from data obtained by manually inspecting a plurality of wafers.Type: GrantFiled: November 28, 2000Date of Patent: February 4, 2003Assignee: MEMC Electronic Materials, Inc.Inventor: David John Ruprecht
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Publication number: 20030008435Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.Type: ApplicationFiled: June 21, 2002Publication date: January 9, 2003Applicant: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Jeffrey L. Libbert
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Publication number: 20030008421Abstract: A process is disclosed for making a silicon wafer with low and uniform surface stress by growing at least approximately 8 angstroms of silicon oxide thereon to produce a wafer for use as a control wafer in ion implantation. The process involves the steps of (a) subjecting a feed wafer substantially free of oxide or having less than approximately 4 angstroms of silicon oxide thereon to hydrogen termination of the silicon surface; or (b) subjecting such a feed wafer to said hydrogen termination followed by subjecting the resulting wafer to treatment with an oxidant having a standard reduction potential less than approximately 1.77 volts; the wafer resulting from either step (a) or (b) having a TWO reading less than approximately 30 across the entire wafer.Type: ApplicationFiled: November 21, 2001Publication date: January 9, 2003Applicant: MEMC Electronic Materials, Inc.Inventor: Larry W. Shive
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Patent number: 6503322Abstract: An electrical resistance heater for use in a crystal puller used for growing monocrystalline silicon ingots according to the Czochralski method comprises a heating element sized and shaped for placement in a housing of the crystal puller generally above a crucible in spaced relationship with the outer surface of the growing ingot for radiating heat to the ingot as it is pulled upward in the housing relative to the molten silicon. The heating element has an upper end and a lower end. The lower end of the heating element is disposed substantially closer to the molten silicon than the upper end when the heating element is placed in the housing. The heating element is constructed such that the heating power output generated by the heating element gradually increases from the lower end to the upper end of the heating element.Type: GrantFiled: October 19, 2000Date of Patent: January 7, 2003Assignee: MEMC Electronic Materials, Inc.Inventors: Richard G. Schrenker, William L. Luter
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Patent number: 6500255Abstract: A process for growing a single crystal silicon ingot having an axially symmetric region substantially free of agglomerated intrinsic point defects. The ingot is grown generally in accordance with the Czochralski method; however, the manner by which the ingot is cooled from the temperature of solidification to a temperature which is in excess of about 900° C. is controlled to allow for the diffusion of intrinsic point defects, such that agglomerated defects do not form in this axially symmetric region. Accordingly, the ratio v/G0 is allowed to vary axially within this region, due to changes in v or G0, between a minimum and maximum value by at least 5%.Type: GrantFiled: May 11, 2001Date of Patent: December 31, 2002Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Vladimir Voronkov, Paolo Mutti
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Patent number: 6497403Abstract: A holder for holding a semiconductor wafer for treatment in wafer treating apparatus including a plurality of supports for generally point support of the wafer at a plurality of points on the wafer. Each support bears a fraction of weight of the wafer and is movable up and down and subject to force biasing it to move upward. The total of the forces exerted on the supports biasing them upward is adapted to counterbalance the weight of the wafer.Type: GrantFiled: December 28, 2000Date of Patent: December 24, 2002Assignee: MEMC Electronic Materials, Inc.Inventor: Michael J. Ries
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Publication number: 20020189528Abstract: The present invention relates to a process for the treatment of Czochralski single crystal silicon wafers to dissolve existing oxygen clusters and precipitates, while preventing their formation upon a subsequent oxygen precipitation heat treatment. The process comprises (i) heat-treating the wafer in a rapid thermal annealer at a temperature of at least 1150° C. in an atmosphere having an oxygen concentration of at least 1000 ppma, or alternatively (ii) heat-treating the wafer in a rapid thermal annealer at a temperature of at least about 1150° C. and then controlling the rate of cooling from the maximum temperature achieved during the heat-treatment through a temperature range in which vacancies are relatively mobile in order to reduce the number density of vacancies in the single crystal silicon to a value such that oxygen precipitates will not form if the wafer is subsequently subjected to an oxygen precipitation heat-treatment.Type: ApplicationFiled: August 13, 2002Publication date: December 19, 2002Applicant: MEMC Electronic Materials, Inc.Inventor: Robert J. Falster
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Publication number: 20020179006Abstract: The process relates to a process for nucleating and growing oxygen precipitates in a silicon wafer. The process includes subjecting a wafer having a non-uniform concentration of crystal lattice vacancies with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer to a non-isothermal heat treatment to form of a denuded zone in the surface layer and to cause the formation and stabilization of oxygen precipitates having an effective radial size 0.5 nm to 30 nm in the bulk layer. The process optionally includes subjecting the stabilized wafer to a high temperature thermal process (e.g. epitaxial deposition, rapid thermal oxidation, rapid thermal nitridation and etc.) at temperatures in the range of 1000° C. to 1275° C. without causing the dissolution of the stabilized oxygen precipitates.Type: ApplicationFiled: April 22, 2002Publication date: December 5, 2002Applicant: MEMC Electronic Materials, Inc.Inventors: Marco Borgini, Daniela Gambaro, Marco Ravani, Michael J. Ries, Laura Sacchetti, Robert W. Standley, Robert J. Falster, Mark G. Stinson
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Publication number: 20020174828Abstract: A process for manufacturing silicon wafers that reduces the size of silicon wafer surface and/or sub-surface defects without the forming excessive haze. The process entails cleaning the front surface of the silicon wafer at a temperature of at least about 1100 ° C. by exposing the front surface to a cleaning ambient comprising H2, HF gas, or HCl gas to remove silicon oxide from the front surface and exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100 ° C. to a vacuum or an annealing ambient consisting essentially of a mono-atomic noble gas selected from the group consisting of He, Ne, Ar, Kr, and Xe to facilitate the migration of silicon atoms to the exposed agglomerated defects without substantially etching silicon from the front surface of the heated silicon wafer.Type: ApplicationFiled: March 29, 2002Publication date: November 28, 2002Applicant: MEMC Electronic Materials, Inc.Inventors: Jiri L. Vasat, Andrei Stefanescu, Thomas A. Torack, Gregory M. Wilson
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Patent number: 6485992Abstract: A process is disclosed for making a silicon wafer with low and uniform surface stress by growing at least approximately 8 angstroms of silicon oxide thereon to produce a wafer for use as a control wafer in ion implantation. The process involves the steps of (a) subjecting a feed wafer substantially free of oxide or having less than approximately 4 angstroms of silicon oxide thereon to hydrogen termination of the silicon surface; or (b) subjecting such a feed wafer to said hydrogen termination followed by subjecting the resulting wafer to treatment with an oxidant having a standard reduction potential less than approximately 1.77 volts; the wafer resulting from either step (a) or (b) having a TWO reading less than approximately 30 across the entire wafer.Type: GrantFiled: November 21, 2001Date of Patent: November 26, 2002Assignee: MEMC Electronic Materials, Inc.Inventor: Larry W. Shive
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Publication number: 20020170631Abstract: A process for heat-treating a single crystal silicon wafer to dissolve agglomerated vacancy defects and to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step is disclosed. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a thermal anneal to dissolve agglomerated vacancy defects present in a stratum extending from the front surface toward the center of the wafer. The annealed wafer is then heat-treated to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon.Type: ApplicationFiled: February 4, 2002Publication date: November 21, 2002Applicant: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Martin Jeffrey Binns, Harold W. Korb
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Publication number: 20020170485Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C., and (iii) a cooling rate of the crystal from a solidification temperature to about 1,050° C., in order to cause the formation of an axially symmetrical segment which is substantially free of agglomerated intrinsic point defects.Type: ApplicationFiled: April 30, 2002Publication date: November 21, 2002Applicant: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Joseph C. Holzer, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
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Patent number: 6482263Abstract: A heat shield assembly is adapted for location within a crystal puller, with respect to a crucible, above molten source material held by the crucible in the puller. The heat shield assembly has a central opening sized and shaped for surrounding the ingot as the ingot is pulled from the molten material and is generally interposed between the ingot and the crucible as the ingot is pulled from the source material. The heat shield assembly comprises an outer reflector having an inner surface and an outer surface in generally opposed, spaced relationship with a side wall of the crucible, and an inner reflector located inward of the outer reflector. The inner reflector is constructed of a material having a low emissivity and has an outer surface in generally opposed relationship with the inner surface of the outer reflector.Type: GrantFiled: October 6, 2000Date of Patent: November 19, 2002Assignee: MEMC Electronic Materials, Inc.Inventors: Lee W. Ferry, Steven L. Kimbel, Kirk D. McCallum, Richard G. Schrenker
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Patent number: 6482269Abstract: A process for removing a metallic contaminant from a nonpatterned silicon wafer. In the process, the wafer is annealed by immersing it for at least about 0.1 hours in an acidic solution which is heated to a temperature of at least about 125° C. in order to diffuse the metal to the surface of the wafer. As the diffused metal reaches the wafer surface, it is oxidized and complexed by the acidic solution and removed from the wafer surface.Type: GrantFiled: May 21, 1998Date of Patent: November 19, 2002Assignee: MEMC Electronic Materials, Inc.Inventors: Larry W. Shive, Carissima M. Vitus
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Patent number: 6479386Abstract: A process for forming a semiconductor wafer which is single side polished improves nanotopology and flatness of the polished wafer. The process reduces the effect of back side surface features, such as edge ring phenomena and back side laser marks, on nanotopology, thereby improving oxide layer uniformity for chemical/mechanical planarization (CMP) processing, and flatness on the polished front side of the wafer after polishing. The wafer is mounted on a polishing block by wax. The edge ring causes certain deformation and stress in the wafer upon mounting, which is held by the wax. After mounting, the wax is heated to allow the wafer to relax, removing the stress, without degrading the bond of the wafer to the polishing block. The wafer is polished and removed from the polishing blocks. The polished surface substantially retains its shape after being de-mounted from the block.Type: GrantFiled: February 16, 2000Date of Patent: November 12, 2002Assignee: MEMC Electronic Materials, Inc.Inventors: Kan-Yin Ng, Yun-Biao Xin, Henry Erk, Darrel Harris, James Jose, Stephen Hensiek, Gene Hollander, Dennis Buese, Giovanni Negri
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Patent number: 6461427Abstract: A process for preparing doped molten silicon for use in a single silicon crystal growing process is disclosed. Polysilicon is doped with barium and melted in a silica crucible containing less than about 0.5% gases insoluble in silicon. During melting and throughout the crystal growing process the barium acts as a devitrification promoter and creates a layer of devitrified silica on the inside crucible surface in contact with the melt resulting in a lower level of contaminants in the melt and grown crystal.Type: GrantFiled: May 17, 2001Date of Patent: October 8, 2002Assignee: MEMC Electronic Materials, Inc.Inventors: Richard Joseph Phillips, Steven Jack Keltner, John Davis Holder
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Publication number: 20020142619Abstract: A process for etching a silicon wafer is disclosed. The process comprises oxidizing silicon with permanganate ions and stripping the silicon oxide with hydrofluoric acid, in the presence of a non-oxidizable acid and typically a surfactant. The present process affords a means to more consistently obtain a silicon wafer having improved gloss or smoothness, while minimizing both the amount of silicon removed from the wafer surface and the cost of the etching process.Type: ApplicationFiled: January 4, 2002Publication date: October 3, 2002Applicant: MEMC Electronic Materials, Inc.Inventors: Alexis Grabbe, Thomas E. Doane
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Publication number: 20020139294Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process comprises controlling growth conditions, such as growth velocity, v, instantaneous axial temperature gradient, G0, and the cooling rate, within a range of temperatures at which silicon self-interstitials are mobile, in order to prevent the formation of these agglomerated defects. In ingot form, the axially symmetric region has a width, as measured from the circumferential edge of the ingot radially toward the central axis, which is at least about 30% the length of the radius of the ingot. The axially symmetric region additionally has a length, as measured along the central axis, which is at least about 20% the length of the constant diameter portion of the ingot.Type: ApplicationFiled: April 30, 2002Publication date: October 3, 2002Applicant: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Joseph C. Holzer
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Patent number: 6458202Abstract: A Czochralski method of producing a single crystal silicon ingot having a uniform thermal history. In the process, the power supplied to the side heater is maintained substantially constant throughout the growth of the main body and end-cone of the ingot, while power supplied to a bottom heater is gradually increased during the growth of the second half of the main body and the end-cone. The present process enables an ingot to be obtained which yields wafers having fewer light point defects in excess of about 0.2 microns, while having improved gate oxide integrity.Type: GrantFiled: June 19, 2000Date of Patent: October 1, 2002Assignee: MEMC Electronic Materials, Inc.Inventors: Makoto Kojima, Yasuhiro Ishii
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Patent number: 6454851Abstract: A method and apparatus for preparing molten silicon melt from polycrystalline silicon in a crystal pulling apparatus entails loading an amount of polycrystalline silicon loaded into the crucible less than a predetermined total amount of polycrystalline silicon to be melted. The crucible is heated to form a partially melted charge in the crucible having an island of unmelted polycrystalline silicon exposed above an upper surface of melted silicon. Granular polycrystalline silicon is fed from a feeder onto the island of unmelted polycrystalline silicon until the predetermined total amount of polycrystalline silicon has been loaded into the crucible. The position of the island relative to the crucible side wall is electronically determined as granular polycrystalline silicon is fed onto the island.Type: GrantFiled: November 9, 2000Date of Patent: September 24, 2002Assignee: MEMC Electronic Materials, Inc.Inventors: Robert H. Fuerhoff, Mohsen Banan, John D. Holder