Abstract: A memory system includes a memory controller having a bank command scheduler implemented in a hardware logic block and a power budget controller including a power budget register and a credit register. The hardware logic block is able to determine a command in a queue to be transmitted to a memory bank over a channel, estimate a power consumption value for the command, and query the power budget controller to determine if the power consumption value is within a threshold. If the power consumption value is within the threshold, the hardware logic block receives a grant response from the power budget controller, adds the power consumption value to the credit register value, transmits the command over the channel, and transmits a signal to the power budget controller indicating that the command has been executed and that the power consumption value should be subtracted from the credit register value.

Abstract: A semiconductor memory device according to an embodiment includes: a row decoder and a memory cell array including a first block. The first block includes: a first region, a second region adjacent to the first region in the first direction, and a third region configured to connect the first region and the second region- The memory cell array further includes: a first insulating layer buried in a first trench between the first region and the second region and in contact with the third region; a first contact plug provided in the first insulating layer and electrically connected to the row decoder; and a first interconnect configured to connect a selection gate line and the first contact plug.

Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on a first read operation on the flash memory with a first reference voltage. The circuit may be configured to generate soft information based on the estimated slope information. The circuit may be configured to decode a result of a second read operation on the flash memory based on the soft information.

Abstract: A memory system includes a non-volatile memory having a plurality of memory chips, a plurality of switches provided for each of the memory chips for switching on and off supply of power to the corresponding memory chip, and a memory controller configured to control the switches and data access to the non-volatile memory. The memory controller is further configured to determine whether there is a first memory chip among the plurality of memory chips that has no data item stored therein with an elapsed time from a most recent access thereof that is less than a threshold value, and if so, turn off the supply of power to the first memory chip while maintaining the supply of power to the plurality of memory chips other than the first memory chip.

Abstract: According to one embodiment, there is provided a semiconductor storage device including N word lines, M bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. M is an integer of two or greater. The M bit lines intersect with the word lines. The multiple memory cells are placed at positions where the word lines and the bit lines intersect. The memory cell stores binary data. The read circuit is connected to the M bit lines. The read circuit is able to detect levels of a multi-ary signal.

Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.

Abstract: Systems and methods for two-layered or a two-phase deterministic inter-process communication (IPC) scheduling for input output deterministic (IOD) sets also referred to as non-volatile memory (NVM) sets in a solid state drive (SSD) system are provided. In various embodiments, an SSD controller includes an IPC scheduler comprising a first layer NVM set scheduler and a second layer fair share scheduler, configured to receive information messages for NVM sets, operable to prioritize the information messages in IPC queues, and generate an IPC pipeline to be processed for I/O operations.

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.

Abstract: A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

Abstract: Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.

Abstract: According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.

Abstract: According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device.