Patents Assigned to Micronics
  • Patent number: 12219883
    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Stephen W. Russell, Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer, Lorenzo Fratin
  • Patent number: 12217159
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM) to store parameters of an artificial neural network (ANN). The device can generate random bit errors to simulate compromised or corrupted memory cells in a portion of the RAM accessed during computations of a first ANN output. A second ANN output is generated with the random bit errors applied to the data retrieved from the portion of the RAM. Based on a difference between the first and second ANN outputs, the device may adjust the ANN computation to reduce sensitivity to compromised or corrupted memory cells in the portion of the RAM. For example, the sensitivity reduction may be performed through ANN training using machine learning.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Poorna Kale
  • Patent number: 12219783
    Abstract: Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material and the channel material includes a second, different material.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy
  • Patent number: 12219757
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material-string structures of memory cells extend through the insulative tiers and the conductive tiers. The channel-material-string structures individually comprise an upper portion above and joined with a lower portion. Individual of the channel-material-string structures comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method are disclosed.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli
  • Patent number: 12218079
    Abstract: Semiconductor devices having reinforcement structures configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate can include a base structure and a reinforcement structure at least partially within a die shadow region of the substrate. The reinforcement structure can be at least partially surrounded by the base structure. The reinforcement structure has a higher stiffness than the base structure.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Koustav Sinha, Shams U. Arifeen, Christopher Glancey
  • Patent number: 12217816
    Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include a first transmission line and a second transmission line located over one another. A via is shown connecting the first transmission line and a second transmission line wherein a first side of the via and a side of the second transmission line are coplanar. A via is also shown connecting the first transmission line and a second transmission line wherein the second transmission line tapers downward from a line width to a via width.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Keizo Kawakita
  • Patent number: 12216915
    Abstract: Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Animesh R. Chowdhury, Kishore K. Muchherla, Nicola Ciocchini, Akira Goda, Jung Sheng Hoei, Niccolo′ Righetti, Jonathan S. Parry
  • Patent number: 12218119
    Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Chan H. Yoo
  • Patent number: 12216573
    Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
  • Patent number: 12217799
    Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Paing Z. Htet, Akira Goda, Eric N. Lee, Jeffrey S. McNeil, Junwyn A. Lacsao, Kishore Kumar Muchherla, Sead Zildzic, Violante Moschiano
  • Patent number: 12216584
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains
  • Patent number: 12219782
    Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Srivatsan Venkatesan, Fabio Pellizzer
  • Patent number: 12217796
    Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Justin Eno, Sean S. Eilert, Ameen D. Akel, Kenneth M. Curewitz
  • Patent number: 12216806
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which self-lock security may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a predefined event associated with the memory device operation. The predefined event may include an operating parameter of the memory device, one or more commands directed to the memory device, or both. The memory device may monitor the predefined event and determine that the predefined event satisfies a threshold. The threshold may be related to a time elapsed since the predefined event has occurred or a certain pattern in the one or more commands. Subsequently, the memory device may disable a circuit configured to access the fuse array based on the determination such that an access to the fuse array is no longer allowed.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Nathaniel J. Meier, Brenton P. Van Leeuwen
  • Patent number: 12219784
    Abstract: Methods for, apparatuses with and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a first dielectric material positioned between the first plurality and the second plurality of word line plates, the first dielectric material extending in a serpentine shape over the substrate; a conformal material positioned between the first dielectric material and the first and second plurality of word line plates, respectively; a plurality of spacers; a plurality of pillars coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Paolo Fantini, Fabio Pellizzer
  • Patent number: 12218101
    Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Chan H. Yoo, Mark E. Tuttle
  • Patent number: 12218056
    Abstract: Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Kinney
  • Patent number: 12217788
    Abstract: Apparatuses and methods for controlling sense amplifier operation are described. An example method includes providing a control signal having a first high logic level voltage to activate isolation switches of a sense amplifier. The control signal transitions from the first high logic level voltage to an inactive voltage to deactivate the isolation switches of the sense amplifier before accessing a memory cell. The control signal is provided having the first high logic level voltage to activate the isolation switches of the sense amplifier after accessing the memory cell. The control signal is increased from the first high logic level voltage to a second high logic level voltage.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, John P. Behrend
  • Patent number: 12216529
    Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Jian Huang, Zhenming Zhou, Zhongguang Xu, Murong Lang
  • Patent number: 12219762
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises sacrificial material of different composition from the first-tier material there-above and from the second-tier material tier there-above. The sacrificial material is of different composition from that of an uppermost portion of the conductor material of the conductor tier.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins