Patents Assigned to Micronics
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Patent number: 12224201Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.Type: GrantFiled: January 4, 2024Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Si-Woo Lee, Byung Yoon Kim
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Patent number: 12224724Abstract: An amplifier may include multiple transistors with two transistors having their gates tied together via a common connection. The amplifier may utilize a local common mode feedback resistor as part of the amplifier. The local common mode feedback resistor may be coupled between the common connection and respective terminals of two transistors of multiple transistors. The local common mode feedback resistor may include a group of resistors coupled in series. The local common mode feedback resistor may also include a metal oxide semiconductor (MOS) resistor coupled in parallel with one or more of the first group of resistors. In the local common mode feedback, the first MOS resistor provides different levels of resistance to different process corners to reduce overshoot when the amplifier is enabled.Type: GrantFiled: July 15, 2021Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventor: Wei Lu Chu
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Patent number: 12223994Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.Type: GrantFiled: March 15, 2024Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney
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Patent number: 12224310Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.Type: GrantFiled: December 6, 2023Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Masihhur R. Laskar, Nicholas R. Tapias, Darwin Franseda Fan, Manuj Nahar
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Patent number: 12223099Abstract: A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.Type: GrantFiled: March 28, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Seth A. Eichmeyer, Christopher G. Wieduwilt, Matthew D. Jenkinson
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Patent number: 12222869Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.Type: GrantFiled: August 30, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventor: Steven Jeffrey Wallach
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Patent number: 12223999Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.Type: GrantFiled: June 29, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: William Chad Waldrop, David R. Brown, Guy S. Perry, IV
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Patent number: 12224240Abstract: A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.Type: GrantFiled: August 9, 2021Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: S M Istiaque Hossain, Indra V. Chary, Anilkumar Chandolu, Sidhartha Gupta, Shuangqiang Luo
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Patent number: 12223208Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.Type: GrantFiled: November 20, 2023Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Daniel J. Hubbard, Roy Leonard
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Patent number: 12225721Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Spaced insulator-material bodies are formed in and longitudinally-along opposing sides of individual of the memory-block regions in a lowest of the first tiers. After forming the spaced insulator-material bodies, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.Type: GrantFiled: June 16, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: John D. Hopkins, Nancy M. Lomeli
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Patent number: 12223184Abstract: Methods, systems, and devices for distributed power up for a memory system are described. The method may include a memory system receiving, from a host system, a command to initialize a set of memory devices included in a memory system. Upon receiving the command, the memory system may select a first memory device from the set of memory devices and read, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device. The memory system may then read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of the set of memory devices.Type: GrantFiled: May 5, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventor: Giuseppe Cariello
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Patent number: 12223204Abstract: Methods, systems, and devices for memory-aligned access operations are described. A target packet size based on a quantity of physical pages addressable by individual first-level pages of a first-level page table for mapping logical address to respective physical pages may be indicated to a host system. A buffer may be configured based on the target packet size and data for an application at the host system and associated with the target packet size may be stored in the buffer. Based on a utilization threshold of the buffer being reached, a set of data stored in the buffer and having the target packet size may be written to a memory device, where a set of physical addresses for storing the set of data may be identified based on a second-level entry of a second-level page.Type: GrantFiled: December 13, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Luca Porzio, Dionisio Minopoli, Olivier Duval
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Patent number: 12223995Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.Type: GrantFiled: August 30, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: John Christopher Sancon, Kang-Yong Kim, Yang Lu, Hyun Yoo Lee
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Patent number: 12225130Abstract: The disclosure relates to improvements in secure channel establishment. In some aspects, the techniques described herein relate to a method including: issuing, by a client device to a server, a request to establish a secure connection; receiving, by the client device, a response to the request to establish a secure connection from the server, the response including a digital certificate associated with a public key stored by the server, the public key used to establish a symmetric key; validating, by the client device, the digital certificate; and computing, by the client device, a shared secret using the public key stored by the server and a private key generated by the client device.Type: GrantFiled: January 14, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventor: Zhan Liu
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Patent number: 12224037Abstract: Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.Type: GrantFiled: June 14, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Manami Senoo, Hidekazu Noguchi, Yoshio Mizukane
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Patent number: 12224017Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.Type: GrantFiled: September 12, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Nagendra Prasad Ganesh Rao, Paing Z. Htet, Sead Zildzic, Jr., Thomas Fiala, Jian Huang, Zhenming Zhou
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Patent number: 12222805Abstract: A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.Type: GrantFiled: February 16, 2023Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventor: David Matthew Springberg
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Patent number: 12222835Abstract: Systems and methods described herein may enable memory maintenance operations to be performed on a memory device in compliance with a time interval having a duration based on a temperature of the memory device. A system may include a memory device and a memory controller communicatively coupled to the memory device. The memory controller may receive a temperature measurement indicative of a present temperature of the memory device and determine a memory management interval based on the temperature measurement. The memory controller may perform a memory management operation based on the memory management interval. Sometimes, the memory controller powers on the memory device to perform the memory management operation on the memory device.Type: GrantFiled: January 13, 2022Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Angelo Visconti, John David Porter
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Patent number: 12224275Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.Type: GrantFiled: September 29, 2021Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventor: Harutaka Makabe
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Patent number: 12222806Abstract: Data protection with error correction/detection capabilities can be provided on a cache line basis. When provided on a cache line basis to collectively protect the cache line data, the error correction/detection capabilities can be provided with fewer number of bits (e.g., error correction code (ECC) and/or cyclic redundancy check (CRC) bits) as compared to providing the same error correction/detection capabilities individually on a subset of the cache line data.Type: GrantFiled: June 28, 2023Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Marco Sforzin, Paolo Amato