Patents Assigned to Micronics
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Patent number: 12223190Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.Type: GrantFiled: September 19, 2023Date of Patent: February 11, 2025Assignee: Micron Technology, Inc.Inventors: Patrick R. Khayat, Steven Michael Kientz, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu
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Publication number: 20250045198Abstract: Provided is a memory device, a method and a system that includes a host in communication with a system memory having a driver that creates commands for writing and reading data, and the memory device in communication with the host that includes a memory array including a plurality of memory components, a device attached memory including a submission queue and a completion queue for receiving commands from the driver, and a device controller configure to communicate with the device attached memory, the host and the plurality of memory components, such that the device controller receives an interface or link from the driver indicative of commands being placed into the submission queue, and automatically executes any pending commands therein for completion.Type: ApplicationFiled: May 30, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Rohit SEHGAL, Vishal TANNA, Eishan MIRAKHUR, Satheesh Babu MUTHUPANDI, Rajinikanth PANDURANGAN
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Publication number: 20250045161Abstract: Provided is a system configured for connecting to a host, including a memory protocol unit (MPU) configured for connecting one of at least two switch paths within the redundant array of independent devices (RAID) fabric to the host. The system also includes a RAID fabric including two or more leaf switches, each leaf switch including a routing processor coupled to the MPU along a respective one of the two switch paths, and a cluster of fault tolerant engines coupled to the routing processor, and a cluster of fabric fault tolerant CXL devices, each CXL device (i) coupled to a corresponding one of the fault tolerant engines and (ii) including a lock controller. The lock controller is configured to limit modifications to a parity group in the cluster of fabric fault tolerant CXL devices created via write requests and occurring during a single instance in time.Type: ApplicationFiled: June 4, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Tony M. BREWER, Craig WARNER
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Publication number: 20250046359Abstract: Apparatuses and techniques for controlling usage-based disturbance mitigation are described. In an example aspect, usage-based disturbance mitigation is performed between activation and precharging of a row. More specifically, usage-based disturbance circuitry performs an array counter update procedure while the row is active. The techniques for controlling usage-based disturbance mitigation control timing of the array counter update procedure at a multi-bank level or a local-bank level. Additionally, the techniques for controlling usage-based disturbance mitigation control a timing of a precharging operation to ensure completion of the array counter update procedure. The techniques for controlling usage-based disturbance mitigation are not limited to the array counter update procedure and can generally be applied to other aspects of usage-based disturbance mitigation, such as bit-error detection and/or correction.Type: ApplicationFiled: June 13, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Yang Lu, Mark Kalei Hadrick, Donald Morgan
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Publication number: 20250045165Abstract: Systems, methods, and computer-readable storage devices can include fabric networks for isolating and correcting failures in the fabric network and device failures. The fabric network connects to a group of devices and a host. The group of devices includes at least a target data device, other data devices, and a parity device. A redundant array of independent devices (RAID) engine, which is coupled to the one group of devices, performs an access operation. The fault tolerant engine is provided in a leaf switch of the fabric network. A routing processor determines a path for a request received from the host to the target data device. The routing processor is coupled to the fault tolerant engine, and the routing processor is provided in the leaf switch.Type: ApplicationFiled: June 4, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Tony M. BREWER, Craig WARNER
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Publication number: 20250045153Abstract: Provided herein is a memory system including logical to physical memory address translation logic to build up a minimum address space containing a memory device address with defects, the translation being based on memory correction attempts. For each correction attempt, the logical address is first translated to a memory device physical address and bit positions at the physical address are compared with an existing error bit pattern to determine if marking should be applied to the memory device. If the bit positions do not match the existing error bit pattern, but errors are corrected from the marked memory device, the existing error bit pattern will be updated to reflect a new error bit pattern.Type: ApplicationFiled: July 26, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Joseph M. McCRATE, Kirthi SHENOY, Marco SFORZIN, Brian M. TWAIT
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Publication number: 20250047309Abstract: A wireless device includes a sensor configured to receive input data, an antenna configured to transmit a radio frequency (RF) signal that is based at least in part on the input data, and one or more processing units coupled with the sensor and operable, during an active time period, to process the input data using a single neural network for a plurality of processing stages. The plurality of processing stages including a source data processing stage and communication processing stages.Type: ApplicationFiled: February 21, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Fa-Long LUO, Jaime CUMMINS
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Publication number: 20250046358Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.Type: ApplicationFiled: October 21, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventor: Durai Vishak Nirmal Ramaswamy
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Publication number: 20250047320Abstract: A system includes a first wireless communication device comprising a first baseband processor neural network configured to process at least part of data for transmission to a second wireless communication device according to a collaborative processing configuration while collaborative processing is enabled to generate a first radio frequency (RF) signal. The first wireless communication device is configured to transmit the first RF signal. The system further includes a third wireless communication device comprising a second baseband processor neural network configured to, while the collaborative processing is enabled, process at least part of the data for transmission to the second wireless communication device according to a collaborative processing configuration to generate a second RF signal. The third wireless communication device is configured to transmit the second RF signal in collaboration with transmission of the first RF signal by the first baseband processor.Type: ApplicationFiled: February 21, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Fa-Long Luo, Jaime Cummins
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Publication number: 20250044952Abstract: There are provided a system and a method for maintaining the integrity of a memory component that includes receiving, by a memory controller, a plurality of memory requests including at least one write request, allocating a data block into a buffer cache to cache the at least one write request, detecting whether sufficient time has elapsed beyond a predetermined threshold, in response to sufficient time having elapsed beyond the predetermined threshold, flagging a backend memory as being available; and in response to the flagging, fetching the at least one write request to write data to the memory component.Type: ApplicationFiled: June 26, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Edmund GIESKE, Dhawal BAVISHI, Robert M. WALKER
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Publication number: 20250044951Abstract: There are provided a system and a method for write or store driven buffer cache memory for a Reliable Array of Independent Disks (RAID)-protected memory. For example, there is provided a system that can include a RAID subsystem configured to maintain the integrity of a section of a memory. The system can further include a buffer memory communicatively coupled to the RAID subsystem. And the RAID subsystem may be configured to limit a frequency of RAID access memory command amplification by accessing the buffer memory the subsystem is performing an operation configured to maintain the integrity of the section of the memory.Type: ApplicationFiled: June 26, 2024Publication date: February 6, 2025Applicant: Micron Technology, Inc.Inventors: Edmund GIESKE, Dhawal BAVISHI, Robert M. WALKER
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Patent number: 12216906Abstract: Techniques are provided for operating a memory package and more specifically to increasing bandwidth of a system having stacked memory. In an example, a system can include a storage device having a first type of volatile memory and a second type of volatile memory, and a host device coupled to the storage device. The host device can issue commands to the storage device to store and retrieve information of the system. The host device can include a memory map of the storage device and latency information associated with each command of the commands. The host can sort and schedule pending commands according to the latency information and can intermix commands for the first type of volatile memory and commands for the second type of volatile memory to maintain a high utilization or efficiency of a data interface between the host device and the storage device.Type: GrantFiled: September 11, 2022Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 12216586Abstract: Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.Type: GrantFiled: January 5, 2024Date of Patent: February 4, 2025Assignee: MICRON TECHNOLOGY, INC.Inventors: Cagdas Dirik, Robert M. Walker
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Patent number: 12217801Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.Type: GrantFiled: December 7, 2022Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Vinh Q. Diep, Yingda Dong, Ching-Huang Lu
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Patent number: 12216905Abstract: Techniques are described herein for performing a flush operation for a write booster buffer of a memory system. The flush operation may include swapping valid blocks in the write booster buffer for invalid blocks in a storage space of the memory system. After swapping the blocks, the memory system may transfer the information from a first type of blocks that were formerly assigned to the write booster buffer to a second type of blocks in the storage space. In such a flush operation, space is made available in the write booster buffer with less latency than it would take to transfer information between blocks, thereby improving the performance of the write booster mode.Type: GrantFiled: March 19, 2021Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Xing Wang, Wenyu Li, Xiaolai Zhu, Xu Zhang
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Patent number: 12218681Abstract: A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.Type: GrantFiled: September 21, 2022Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Leon Zlotnik, Eyal En Gad
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Patent number: 12218008Abstract: Some embodiments include apparatuses and methods of forming the apparatuses.Type: GrantFiled: May 23, 2023Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Kar Wui Thong, Harsh Narendrakumar Jain, John Hopkins
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Patent number: 12216521Abstract: Methods, systems, and devices for a common error protection buffer for multiple cursors are described. A memory device may receive a command to write data to a memory system. The memory device may assign portions of the data to respective pages of a first cursor and generate error protection data for the assigned data. The memory device may assign the generated error protection data to an error protection buffer common to multiple cursors, for example, by performing an combination operation. The memory device may increment a counter associated with the error protection buffer. The memory device may write a summary of contents of the error protection buffer and a position of each cursor related to the error protection data based on the counter satisfying a threshold. The memory device may perform a readback operation to facilitate garbage collection without losing error protection data.Type: GrantFiled: August 12, 2022Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventor: Rakeshkumar Dayabhai Vaghasiya
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Patent number: 12217806Abstract: Methods, systems, and devices for threshold voltage scans are described. A memory device may receive a configuration for scanning a memory array during a scanning procedure. The memory device may read, during the scanning procedure, one or more memory cells of the memory array using a first voltage value that is indicated by the configuration. The memory device may store, during the scanning procedure, a first value in a first counter in response to reading the one or more memory cells of the memory array. The memory device may determine whether to terminate the scanning procedure in response to one or both of determining that the first quantity of memory cells satisfies a threshold quantity of memory cells or determining that the first voltage value satisfies a threshold voltage value to be scanned.Type: GrantFiled: July 22, 2022Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Aniello Palomba, Ciro Feliciano, Antonio Imperiale
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Patent number: 12216541Abstract: Various embodiments provide block failure protection for a memory sub-system that supports zones, such a memory sub-system that uses a RAIN (redundant array of independent NAND-type flash memory devices) technique for data error-correction. For some embodiments, non-parity zones of a memory sub-system that are filling up at a similar rate are matched together, a parity is generated for stored data from across the matching zones, and the generated parity is stored in a parity zone of the memory device.Type: GrantFiled: January 8, 2024Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventor: Sanjay Subbarao