Abstract: A digital correction circuit for a pipelined analog-to-digital converter (ADC) is disclosed. Compared to the conventional digital correction circuit which uses adders to perform operations in ADC digital correction part and hence needs a rather long operation time, the digital correction circuit of this invention can reduce the time needed in operations in the finial digital correction circuits and thus can optimize operation time, by allocating the operations to a plurality of pipeline stages of second sub-circuits configured to synchronize digital codes, each of which can perform part of the operations only with NAND gates, NOR gates, phase inverters and D-type flip-flops, without needing to use adders.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, which includes: two isolation structures each being formed in a trench; a set of three or more pseudo buried layers formed under each trench with every adjacent two pseudo buried layers of the set being vertically contacted with each other; and a collector region. In this design, the lowermost pseudo buried layers of the two sets are laterally in contact with each other, and the collector region is surrounded by the two isolation structures and the two sets of pseudo buried layers. As the breakdown voltage of a SiGe HBT according to the present invention is determined by the distance between an uppermost pseudo buried layer and the edge of an active region, SiGe HBTs having different breakdown voltages can be achieved. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: A method of inserting dummy patterns is provided. The method includes: determining an applicable area in which dummy patterns shall be inserted and an inapplicable area in which dummy patterns shall not be inserted on a chip; and inserting dummy patterns starting from one side of the inapplicable area and arranging the inserted dummy patterns into circles. The method of the present invention ensures that dummy patters are preferentially inserted around the device that requires protection by dummy patterns, so that good uniformity of chip pattern densities is guaranteed and within-wafer uniformity is improved, thus improving the yield and performance of semiconductor devices.

Abstract: A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.

Abstract: A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution.

Abstract: A superjunction device is disclosed, wherein P-type regions in an active region are not in contact with the N+ substrate, and the distance between the surface of the N+ substrate and the bottom of the P-type regions in the active region is greater than the thickness of a transition region in the N-type epitaxial layer. Methods for manufacturing the superjunction device are also disclosed. The present invention is capable of improving the uniformity of reverse breakdown voltage and overshoot current handling capability in a superjunction device.

Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.

Abstract: A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process.

Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies.

Abstract: The present invention discloses an LDMOS device structure, including a MOS transistor cell, wherein an isolation region is formed on each outer side of both a source region and a drain region of the MOS transistor cell; each isolation region includes a plurality of isolation trenches and isolates the MOS transistor cell from its surroundings; the height of the isolation region is smaller than that of a gate of the MOS transistor cell. The present invention also discloses a manufacturing method of the LDMOS device structure, including forming isolation trenches by lithography and etching processes, then forming isolation regions of SiO2 by depleting silicon between isolation trenches through high-temperature drive-in. The present invention can reduce parasitic capacitance, surface unevenness and difficulty of subsequent process and realize the production of small-size gate devices by forming a thicker field oxide layer and a gap structure of isolation trenches.

Abstract: A terminal structure for superjunction device is disclosed. The terminal structure comprises from inside out at least one P type implantation ring and several P type trench rings formed in an N type epitaxial layer to form alternating P type and N type regions. A channel cut-off ring is formed at the border of the device. The P type implantation ring is formed adjacent to the active area of the device and covers at least one trench ring. A terminal dielectric layer is formed to cover the P type implantation ring and the trench rings. A plurality of field plates are formed above the terminal dielectric layer. Methods of manufacturing terminal structure are also disclosed.

Abstract: A differential amplifier has first and second input terminals (T1, T2), an output terminal, a differential stage connected to the first and second input terminals, and an amplification stage having an input terminal thereof connected to an output terminal of the differential stage and an output terminal thereof connected to the output terminal. The differential stage includes a first differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the output terminal, a second differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the second input terminal (T2), a first current source for supplying current to the first differential pair, a second current source for supplying current to the second differential pair, and a load circuit connected to the output pairs of the first and second differential pairs.

Abstract: A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues.

Abstract: A PN-junction varactor in a BiCMOS process is disclosed which comprises an N-type region, a P-type region and N-type pseudo buried layers. Both of the N-type and P-type regions are formed in an active area and contact with each other, forming a PN-junction; the P-type region is situated on top of the N-type region. The N-type pseudo buried layers are formed at bottom of shallow trench field oxide regions on both sides of the active area and contact with the N-type region; deep hole contacts are formed on top of the N-type pseudo buried layers in the shallow trench field oxide regions to pick up the N-type region. A manufacturing method of PN-junction varactor in a BiCMOS process is also disclosed.

Abstract: A parasitic PIN device in a BiCMOS process is disclosed. The device is formed on a silicon substrate, in which an active region is isolated by shallow trenches. The device includes: an N-type region, consisting of N-type pseudo buried layers respectively formed at the bottom of shallow trench isolation oxide layers and extending into the active region; an I-type region, consisting of an N-type collector implantation region formed in the active region and contacting with the N-type region; a P-type region, consisting of a P-doped intrinsic base epitaxial layer on a surface of the active region and contacting with the I-type region. The device of the present invention has a low insertion loss and a high isolation. A manufacturing method of parasitic PIN device in compatible with existing BiCMOS process is also disclosed.

Abstract: A parasitic PNP bipolar transistor, wherein a base region includes a first and a second region; the first region is formed in an active area, has a depth larger than shallow trench field oxides, and has its bottom laterally extended into the bottom of the shallow trench field oxides on both sides of an active area; the second region is formed in an upper part of the first region and has a higher doping concentration; an N-type and a P-type pseudo buried layer is respectively formed at the bottom of the shallow trench field oxides; a deep hole contact is formed on top of the N-type pseudo buried layer to pick up the base; the P-type pseudo buried layer forms a collector region separated from the active area by a lateral distance; an emitter region is formed by a P-type SiGe epitaxial layer formed on top of the active area.

Abstract: A method of forming silicide layers is disclosed, the method including: providing a silicon substrate which includes at least one first region and at least one second region; depositing a dielectric layer over the silicon substrate; forming at least one opening having a great width/depth ratio in the dielectric layer above the at least one first region, and forming at least one opening having a small width/depth ratio in the dielectric layer above the at least one second region; depositing a metal and performing a high-temperature annealing to form a thick silicide layer in each of the at least one opening above each of the at least one first region and to form a thin silicide layer in each of the at least one opening above each of the at least one second region; removing the remaining metal not formed into the silicide layers.

Abstract: A stacked inductor with different metal thickness and metal width. The stacked inductor comprises top and bottom metal traces which are aligned with each other. The thickness and width of the top and bottom metal traces are different. The top and bottom metal traces are connected at the end of metal trace with via holes. The inductance is increased with the use of the mutual inductance between top and bottom metal layers The parasitic resistor is reduced due to the difference of the top and bottom metal widths.

Abstract: The present invention discloses a method of manufacturing superjunction structure, which comprises: step 1, grow an N type epitaxial layer on a substrate having a (100) or (110) oriented surface; step 2, etch the N type epitaxial layer to form trenches therein; step 3, fill the trenches by P type epitaxial growth in the trenches by using a mixture of silicon source gas, halide gas, hydrogen gas, and doping gas. By using the manufacturing method according to the present invention, no void or only small voids are formed in the trenches after trench filling.