Abstract: This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process.

Abstract: A superjunction structure with unevenly doped P-type pillars (4) and N-type pillars (2a) is disclosed. The N-type pillars (2a) have uneven impurity concentrations in the vertical direction and the P-type pillars (4) have two or more impurity concentrations distributed both in the vertical and lateral directions to ensure that the total quantity of P-type impurities in the P-type pillars (4) close to the substrate (8) is less than that of N-type impurities in the N-type pillars close to the substrate; the total quantity of P-type impurities in the P-type pillars close to the top of the device is greater than that of N-type impurities in the N-type pillars close to the top. A superjunction MOS transistor and manufacturing method of the same are also disclosed. The superjunction structure can improve the capability of sustaining current-surge of a device without affecting or may even reduce the on-resistance of the device.

Abstract: A bond pad structure for an integrated circuit chip package is disclosed. The bond pad structure includes a top metal layer, a patterned metal layer and an interconnection structure. The patterned metal layer is formed below the top metal layer and includes an annular metal layer and a plurality of metal blocks evenly arranged at a central area of the annular metal layer; the patterned metal layer is connected to the top metal layer through both the annular metal layer and the metal blocks. The interconnection structure is formed below the patterned metal layer and is connected to patterned metal layer only through the annular metal layer. By using the above structure, active or passive devices can be disposed under the bond pad structure and will not be damaged by package stress. An integrated circuit employing the above bond pad structure is also disclosed.

Abstract: A vertical PNP device in a silicon-germanium (SiGe) BiCMOS process is disclosed. The device is formed in a deep N-well and includes a collector region, a base region and an emitter region. The collector region has a two-dimensional L-shaped structure composed of a lightly doped first P-type ion implantation region and a heavily doped second P-type ion implantation region. The collector region is picked up by P-type pseudo buried layers formed at bottom of the shallow trench field oxide regions. A manufacturing method of vertical PNP device in a SiGe BiCMOS process is also disclosed. The method is compatible with the manufacturing processes of a SiGe heterojunction bipolar transistor in the SiGe BiCMOS process.

Abstract: A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region.

Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit.

Abstract: A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.

Abstract: A superjunction device is disclosed, wherein P-type regions in an active region are not in contact with the N+ substrate, and the distance between the surface of the N+ substrate and the bottom of the P-type regions in the active region is greater than the thickness of a transition region in the N-type epitaxial layer. Methods for manufacturing the superjunction device are also disclosed. The present invention is capable of improving the uniformity of reverse breakdown voltage and overshoot current handling capability in a superjunction device.

Abstract: A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance.

Abstract: A method of etching and tilling deep trenches is disclosed, which includes: forming an ONO(oxide-nitride-oxide) sandwich layer on a semiconductor substrate; forming deep trenches by using top oxide of the sandwich layer as a stop layer; removing the top oxide and middle SiN of the sandwich layer; tilling the deep trenches with epitaxial film or polysilicon film; polishing the wafer to get a planarized surface by stopping at the surface of the bottom oxide layer; removing the bottom oxide layer.

Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.

Abstract: This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process.

Abstract: A self-calibration circuit of a nonvolatile memory includes a trimming data storage module, a sense amplifier module, a logic judgment module, and a scanning module. The nonvolatile memory circuit includes a memory cell array and the self-calibration circuit of the reading circuit of the nonvolatile memory. Without requiring an additional fuse or differential unit, the self-calibration circuit of a nonvolatile memory solves a deadlock problem securely and reliably without increasing circuit area and test cost, and be widely applied to OTP, MTP and EEPROM of various processes or various nonvolatile memories such as Flash EEPROM, MRAM, and FeRAM.

Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

Abstract: A sense amplifier and method of implementing includes a reference current generation circuit, which is used for providing a reference current with a settable temperature coefficient for a main circuit of the sense amplifier; the main circuit is used for comparing the reference current with a storage cell current, and distinguishing between 0 and 1 Storage Cell. A method of implementing the sense amplifier that is as below: With an additional current reference circuit, generating and inputting the reference current with a positive/negative/zero temperature coefficient into the main circuit, by mixing a proportional absolute temperature current and a constant current according to different ratios; a storage cell selection tube in a mirror branch of a biased current of the main circuit, so as to constitute a source degeneration circuit, making the biased current change with the power supply voltage and realizing a gain compensation function.

Abstract: A semiconductor integrated circuit design apparatus (100) includes a delay analysis unit (102) which analyzes a static delay in respective paths of a semiconductor integrated circuit, a noise generation unit (104) which generates noise information based on a predetermined noise definition, a voltage fluctuation level analysis unit (106) which analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the noise information, and a timing verification unit (108) which makes the delay analysis unit (102) analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis, wherein the noise generation unit (104) generates noise information on noise applied at predetermined application timing, and the timing verification unit (108) verifies the timing for each noise applied with the predetermined application timing.

Abstract: The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage. The present invention further discloses a method of implementing the decoding circuit and a memory circuit using the decoding circuit.

Abstract: A heat sink 109 is configured by a plate component having a combined structure composed of a recess and a projection formed thereon, wherein the recess is formed by allowing a part of the plate component to be set back from the surface level of the residual region, and the projection is formed on one surface of the plate component with the progress of formation of the recess, so as to be built up above the level of the residual region of the one surface.

Abstract: A semiconductor device 1 includes a semiconductor chip 10 (first semiconductor chip), a semiconductor chip 20 (second semiconductor chip) and a seal ring 30. The semiconductor chip 20 is provided on a surface S1 of the semiconductor chip 10 so as to be spaced apart from the semiconductor chip 10 with a predetermined spacing therebetween. A seal ring 30 is interposed between the semiconductor chip 10 and the semiconductor chip 20. An internal region, which is an inner region of the seal ring 30, and an external region, which is an outer region of the seal ring 30, are provided between the semiconductor chip 10 and the semiconductor chip 20.