Patents Assigned to NEC Electronics
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Publication number: 20110014785Abstract: This method includes an electrode pad forming process for forming an electrode pad on a substrate, a solder bump forming process for forming a solder bump on the electrode pad, at least part of the surface of the solder bump being covered with a flux, and an oxygen exposure process for supplying an oxygen gas having reactive properties, such as an ozone (O3) gas, to the solder bump.Type: ApplicationFiled: June 29, 2010Publication date: January 20, 2011Applicant: NEC Electronics CorporationInventor: Yuji Shimizu
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Publication number: 20110012108Abstract: A semiconductor device includes a cell array and a plurality of process failure detection circuits each having a layout pattern substantially identical to that of a cell of the cell array in a dummy region arranged around the cell array. Each of the process failure detection circuits includes a dummy pattern that equalizes a degree of density/sparsity of a peripheral part of the cell array with that of a central part of the cell array. The process failure detection circuits include a process failure detection circuit having a layout pattern formed with a stricter pattern margin in at least one manufacturing process, compared with the layout pattern of the cell of the cell array.Type: ApplicationFiled: June 29, 2010Publication date: January 20, 2011Applicant: NEC Electronics CorporationInventor: Toru Fujimura
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Publication number: 20110012265Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.Type: ApplicationFiled: June 2, 2010Publication date: January 20, 2011Applicant: NEC Electronics CorporationInventor: Hidenori Egawa
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Patent number: 7872627Abstract: A driving circuit of the display unit includes a driving circuit including a read only memory and a rewritable nonvolatile memory. The rewritable nonvolatile memory stores display quality specifying information for specifying the display quality of a display panel connected to the driving circuit. The read only memory stores the display quality initial information used for initialization of the display quality of an optional display panel. By preferentially using the information stored in the rewritable nonvolatile memory, it is possible to drive the display panel at an optimum display quality in the normal state. Moreover, even when it is impossible to normally read data from the rewritable nonvolatile memory, it is possible to drive the display panel at an initial-state display quality by using the data in the read only memory.Type: GrantFiled: November 18, 2005Date of Patent: January 18, 2011Assignee: NEC Electronics CorporationInventor: Kaito Fushimi
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Publication number: 20110007442Abstract: Provided is a protection circuit that is connected between a power supply terminal and an output terminal, and turns off an output transistor when an abnormality occurs in a system, the output transistor outputting a current to a load connected to the output terminal, the protection circuit including: a first discharge unit that is connected between a gate electrode of the output transistor and the power supply terminal, and discharges an electric charge of the gate electrode until a potential of the gate electrode becomes equal to a power supply potential, when an abnormality occurs in the system, and a second discharge unit that is connected between the gate electrode and a source electrode of the output transistor, and discharges the electric charge of the gate electrode until the potential of the gate electrode becomes equal to an output potential, when an abnormality occurs in the system.Type: ApplicationFiled: June 18, 2010Publication date: January 13, 2011Applicant: NEC Electronics CorporationInventors: Jun Fukuhara, Tsuyoshi Mitsuda
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Publication number: 20110006939Abstract: A resistor string type D/A converter in accordance with an exemplary aspect of the present invention includes a resistor string, switches, a higher-order decoder, a lower-order decoder, and a conversion unit. The resistor string generates a plurality of analog voltages by dividing a voltage between a first reference voltage and a second reference voltage. Each of the switches is provided for a respective one of a plurality of voltage drawing points. The higher-order decoder generates a higher-order control signal according to the value of higher bits of an input digital signal. The lower-order decoder generates a lower-order control signal corresponding to the value of lower bits of the input digital signal. The conversion unit outputs a voltage between a pair of the analog voltage values obtained through a pair of switches based on the lower-order control signal.Type: ApplicationFiled: June 9, 2010Publication date: January 13, 2011Applicant: NEC Electronics CorporationInventor: Koji Hirai
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Publication number: 20110007857Abstract: A communication device includes a current information storage unit 130 that stores the bit boundary signal at each of timings at which a sampling clock is updated, a past information storage unit 140 that takes in and stores a signal stored in the current information storage unit 130 when a variation point of a reception signal is detected, and does not update a signal stored therein when no variation point of the reception signal is detected, and a clock selection unit 44 that selects CLKSEL2 used for the sampling of the reception signal from N-phase clocks based on a signal stored in the current information storage unit 130 when a variation point of the reception signal is detected, and selects CLKSEL3 based on a signal stored in the past information storage unit 140 when no variation point of the reception signal is detected.Type: ApplicationFiled: June 4, 2010Publication date: January 13, 2011Applicant: NEC Electronics CorporationInventors: Shinya Konishi, Norio Arai, Osamu Ohnishi
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Publication number: 20110006797Abstract: Provided are a probe card including a first area group including a plurality of first areas, each including a plurality of probes for input pad and probes for output pad, the first areas being aligned in L rows by M columns (L, M: natural number); and a second area group including a plurality of second areas, each including a plurality of probes for input pad, the second areas being aligned in (L×N) rows by M columns (N: natural number); and the first area group and the second area group are continuously connected in a column direction according to the chip alignment, such that the first areas and the second areas are aligned in {L+(L×N)} rows by M columns.Type: ApplicationFiled: June 8, 2010Publication date: January 13, 2011Applicant: NEC Electronics CorporationInventor: Hitoshi HIRATSUKA
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Patent number: 7869522Abstract: An embodiment of the present invention provides a video signal multiplexing apparatus including a separator separating picture information and additional information from a received video signal, a controller adjusting, if the picture information is out of sync with the additional information, a data amount of the additional information based on a data amount of the picture information in such a manner that the picture information is in sync with the additional information, and a multiplexer multiplexing the encoded data and the additional information the data amount of which has been adjusted.Type: GrantFiled: November 16, 2005Date of Patent: January 11, 2011Assignee: NEC Electronics CorporationInventors: Tomoyuki Okuyama, Kenji Tanaka
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Patent number: 7868257Abstract: A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole.Type: GrantFiled: March 9, 2005Date of Patent: January 11, 2011Assignees: NEC Corporation, NEC Electronics CorporationInventors: Taras Kushta, Kaoru Narita, Hirokazu Tohya, Takanori Saeki, Tomoyuki Kaneko
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Publication number: 20110001509Abstract: A semiconductor integrated circuit device includes: terminals 11a and 11m; first to (2n+1)-th resistive elements (n is an integer of at least 1) (resistive element group 12) connected in series between the terminals 11a and 11m; a selection circuit 14 selecting, assuming that a terminal 11a connected to one end of the first resistive element is a 0th node, a terminal 11m connected to the other end of the (2n+1)-th resistive element is a (2n+1)-th node, and a connection point of the other end of an i-th resistive element (i is an integer from 1 to 2n) and one end of an (i+1)-th resistive element is an i-th node, any one of the 0th to (2n+1)-th nodes and outputting a voltage applied to the selected node; a switch group 15a capable of shorting any 2k-th node (k is an integer from 0 to n); and a switch group 15b capable of shorting any (2k+1)-th node. The 2k-th and (2k+1)-th nodes are shorted, and subsequently, a predetermined voltage is temporarily applied between the terminals 11a and 11m.Type: ApplicationFiled: June 30, 2010Publication date: January 6, 2011Applicant: NEC Electronics CorporationInventor: Toru KIDOKORO
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Publication number: 20110001649Abstract: A differential chopper comparator compares an input signal voltage and a first voltage, and includes a first capacitor, a second capacitor, and a differential amplification unit including a differential amplification circuit. Either the input signal voltage or the first voltage is applied to one end of the first capacitor via a first switch unit. A fixed voltage is applied to one end of the second capacitor via a second switch unit. Either a non-inverting input terminal or an inverting input terminal of the differential amplification circuit is connected to the other end of the first capacitor, and the other terminal is connected to the other end of the second capacitor. An impedance of the first switch unit side viewed from one end of the first capacitor and an impedance of the second switch unit side viewed from one end of the second capacitor are substantially same.Type: ApplicationFiled: June 17, 2010Publication date: January 6, 2011Applicant: NEC Electronics CorporationInventor: Fumio Nakano
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Publication number: 20110001216Abstract: A manufacturing method of a semiconductor device includes: forming a wiring in a first interlayer insulating layer in a first region; etching an surface portion of the first interlayer insulating layer in a second region; forming a plurality of opening portions extended below in the etched region; and forming a lower electrode layer, a dielectric layer, and a common upper electrode in each of the plurality of opening portions to form a plurality of capacitance portions. The step of forming the plurality of capacitance portions, includes: forming the common upper electrode so that an upper surface of the first interlayer insulating layer and an upper surface of the common upper electrode approximately lie in the same plane.Type: ApplicationFiled: June 29, 2010Publication date: January 6, 2011Applicant: NEC Electronics CorporationInventor: Ken Inoue
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Publication number: 20110002164Abstract: A charge pump circuit, whose output is connected to a first node, starts a boosting operation after start of a test period. A load current application circuit supplies a load current to the first node during the test period. A voltage of the first node is a write voltage. A memory circuit stops application of the write voltage to a memory cell during the test period, and applies the write voltage to the memory cell after end of the test period. A high voltage detection unit compares the write voltage and a predetermined voltage to determine whether or not the write voltage is increased to the predetermined voltage. If the write voltage is less than the predetermined voltage at the end of the test period, the high voltage detection unit activates a disable signal. If the disable signal is activated, the charge pump circuit stops the boosting operation.Type: ApplicationFiled: June 29, 2010Publication date: January 6, 2011Applicant: NEC Electronics CorporationInventor: Yoshitaka Soma
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Patent number: 7865021Abstract: A compressed stream decoding apparatus to preventing a disturbance of a display image is disclosed. The compressed stream decoding apparatus includes: a first video data processor decoding an input first compressed video stream based on first reference time information added to the first compressed video stream, and outputting decoded video data based on the first reference time information; and a second video data processor performing alternatively a first processing and a second processing, wherein the first processing is decoding an input second compressed video stream based on second reference time information added to the second compressed video stream and outputting decoded video data based on the second reference time information; and the second processing is outputting the decoded video data decoded by the first video data processor based on the first reference time information.Type: GrantFiled: November 28, 2005Date of Patent: January 4, 2011Assignee: NEC Electronics CorporationInventor: Eiji Tsuboi
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Patent number: 7862736Abstract: Method of cleaning a plasma etching apparatus capable of suppressing variation in line width among wafers in a single lot, and improving throughput in the cleaning process, includes steps of supplying a cleaning gas into a chamber of a plasma etching apparatus; igniting a plasma of the cleaning gas in the chamber; and allowing plasma cleaning to proceed in the chamber, by bringing the cleaning gas in plasma form into contact with a deposit adhered on the inner wall of the chamber so as to etch off the deposit, wherein in the step of plasma cleaning in the chamber, intensity of plasma emission ascribable to the deposit adhered on the inner wall of the chamber is detected in a time-dependent manner, and the plasma cleaning in the chamber is terminated based on changes in the intensity of the plasma emission.Type: GrantFiled: December 5, 2006Date of Patent: January 4, 2011Assignee: NEC Electronics CorporationInventor: Tomoo Nakayama
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Patent number: 7861913Abstract: In a soldering method for mounting a semiconductor device on a wiring board, a plurality of solid-phase solders are provided between the semiconductor device and the wiring board, and are thermally melted to thereby produce a plurality of liquid-phase solders therebetween. A constant force is exerted on the liquid-phase solders by relatively moving the semiconductor device with respect to the wiring board so that an invariable gap is determined between the semiconductor device and the wiring board.Type: GrantFiled: September 19, 2008Date of Patent: January 4, 2011Assignee: NEC Electronics CorporationInventor: Shinichi Miyazaki
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Publication number: 20100332874Abstract: A microcomputer includes a CPU, a standby controller that controls setting of and recovering from a sleep mode of the CPU, an output terminal, a first timer, an output terminal controller, and a second timer. When the first timer performs predetermined time measurement when the CPU is in the sleep mode, the output terminal controller changes the level of the output terminal while maintaining the sleep mode. The second timer starts time measurement when the output terminal controller changes the level of the output terminal in the sleep mode. The standby controller performs recovering from the sleep mode of the CPU when the second timer performs a prescribed time measurement.Type: ApplicationFiled: June 1, 2010Publication date: December 30, 2010Applicant: NEC Electronics CorporationInventor: Yosuke ITABASHI
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Publication number: 20100327964Abstract: A semiconductor device includes: a noise detecting circuit; an input signal delaying circuit; and a mask circuit. The noise detecting circuit detects noise superimposed on an input signal and outputs a mask signal during a predetermined time period. The input signal delaying circuit delays the input signal and outputs a delay signal thereof. The mask circuit outputs an output signal in which the delay signal is masked based on the mask signal.Type: ApplicationFiled: May 28, 2010Publication date: December 30, 2010Applicant: NEC Electronics CorporationInventor: Rika Wakita
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Publication number: 20100330796Abstract: The manufacturing method includes: forming a seed film on a semiconductor chip; forming a photoresist having an opening above an electrode of the semiconductor chip on the seed film; forming a first Au bump on the seed film in the opening by electrolytic plating with a current density of 1.5 A/dm2 or above; grinding a surface of the first Au bump; stripping the photoresist; and removing the seed film by dry-etching.Type: ApplicationFiled: May 28, 2010Publication date: December 30, 2010Applicant: NEC Electronics CorporationInventor: Shigeharu Okaji