Patents Assigned to NEC Electronics
  • Patent number: 8441887
    Abstract: A decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 14, 2013
    Assignee: Shanghai Hua Hong Nec Electronics Company, Ltd.
    Inventors: Nan Wang, Guoyou Feng
  • Patent number: 8421185
    Abstract: A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.
    Type: Grant
    Filed: December 25, 2010
    Date of Patent: April 16, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Company, Limited
    Inventors: Tzuyin Chiu, TungYuan Chu, Wensheng Qian, YungChieh Fan, Donghua Liu, Jun Hu
  • Patent number: 8420495
    Abstract: This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: April 16, 2013
    Assignee: Shanghai Hua Hong Nec Electronics Company, Limited
    Inventors: Tzuyin Chiu, TungYuan Chu, YungChieh Fan, Wensheng Qian, Fan Chen, Jiong Xu, Haifang Zhang
  • Patent number: 8420475
    Abstract: This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 16, 2013
    Assignee: Shanghai Hua Hong Nec Electronics Company, Limited
    Inventors: Tzuyin Chiu, TungYuan Chu, Wensheng Qian, YungChieh Fan, Donghua Liu, Jun Hu
  • Patent number: 8395188
    Abstract: A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: March 12, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Wensheng Qian
  • Patent number: 8378457
    Abstract: A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 19, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Fan Chen, Xiongbin Chen, Wensheng Qian, Zhengliang Zhou
  • Patent number: 8289118
    Abstract: A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: October 16, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Tzuyin Chiu, Xiangming Xu, Miao Cai
  • Patent number: 8273664
    Abstract: A method of etching and tilling deep trenches is disclosed, which includes: forming an ONO(oxide-nitride-oxide) sandwich layer on a semiconductor substrate; forming deep trenches by using top oxide of the sandwich layer as a stop layer; removing the top oxide and middle SiN of the sandwich layer; tilling the deep trenches with epitaxial film or polysilicon film; polishing the wafer to get a planarized surface by stopping at the surface of the bottom oxide layer; removing the bottom oxide layer.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: September 25, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Xiaohua Cheng, Shengan Xiao
  • Patent number: 8227832
    Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 24, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Tzuyin Chiu, Zhengliang Zhou, Xiongbin Chen
  • Patent number: 8222114
    Abstract: This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: July 17, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Company, Limited
    Inventors: Tzuyin Chiu, TungYuan Chu, YungChieh Fan, Wensheng Qian, Fan Chen, Jiong Xu, Haifang Zhang
  • Patent number: 8184490
    Abstract: A self-calibration circuit of a nonvolatile memory includes a trimming data storage module, a sense amplifier module, a logic judgment module, and a scanning module. The nonvolatile memory circuit includes a memory cell array and the self-calibration circuit of the reading circuit of the nonvolatile memory. Without requiring an additional fuse or differential unit, the self-calibration circuit of a nonvolatile memory solves a deadlock problem securely and reliably without increasing circuit area and test cost, and be widely applied to OTP, MTP and EEPROM of various processes or various nonvolatile memories such as Flash EEPROM, MRAM, and FeRAM.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: May 22, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Company, Ltd.
    Inventors: Nan Wang, Xiang Yao
  • Patent number: 8178409
    Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: May 15, 2012
    Assignee: Shanghai Hua Hong Nec Electronics Company, Limited
    Inventors: Shengan Xiao, Feng Han
  • Patent number: 8169834
    Abstract: A sense amplifier and method of implementing includes a reference current generation circuit, which is used for providing a reference current with a settable temperature coefficient for a main circuit of the sense amplifier; the main circuit is used for comparing the reference current with a storage cell current, and distinguishing between 0 and 1 Storage Cell. A method of implementing the sense amplifier that is as below: With an additional current reference circuit, generating and inputting the reference current with a positive/negative/zero temperature coefficient into the main circuit, by mixing a proportional absolute temperature current and a constant current according to different ratios; a storage cell selection tube in a mirror branch of a biased current of the main circuit, so as to constitute a source degeneration circuit, making the biased current change with the power supply voltage and realizing a gain compensation function.
    Type: Grant
    Filed: July 12, 2009
    Date of Patent: May 1, 2012
    Assignee: Shanghai Hua Hong Nec Electronics Company, Ltd.
    Inventors: Nan Wang, Zhaogui Li, Xiang Yao, Zi Wang, Liang Xu
  • Patent number: 8154945
    Abstract: The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage. The present invention further discloses a method of implementing the decoding circuit and a memory circuit using the decoding circuit.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: April 10, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Company, Ltd.
    Inventors: Nan Wang, Guoyou Feng
  • Patent number: 8077466
    Abstract: A heat sink 109 is configured by a plate component having a combined structure composed of a recess and a projection formed thereon, wherein the recess is formed by allowing a part of the plate component to be set back from the surface level of the residual region, and the projection is formed on one surface of the plate component with the progress of formation of the recess, so as to be built up above the level of the residual region of the one surface.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: December 13, 2011
    Assignee: NEC Electronics Corporation
    Inventor: Harumi Mizunashi
  • Patent number: 8039969
    Abstract: A semiconductor device 1 includes a semiconductor chip 10 (first semiconductor chip), a semiconductor chip 20 (second semiconductor chip) and a seal ring 30. The semiconductor chip 20 is provided on a surface S1 of the semiconductor chip 10 so as to be spaced apart from the semiconductor chip 10 with a predetermined spacing therebetween. A seal ring 30 is interposed between the semiconductor chip 10 and the semiconductor chip 20. An internal region, which is an inner region of the seal ring 30, and an external region, which is an outer region of the seal ring 30, are provided between the semiconductor chip 10 and the semiconductor chip 20.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: October 18, 2011
    Assignee: NEC Electronics Corporation
    Inventor: Yoichiro Kurita
  • Publication number: 20110131397
    Abstract: A multiprocessor system includes a memory that stores a program; an address notification register; a first processor; and a second processor, in which the first processor stores address information indicating an address from which the program is executed in the address notification register, when the first processor notifies an interrupt request to the second processor and causes the second processor to execute the program, and the second processor obtains the interrupt request notified from the first processor and the address information stored in the address notification register, and starts to execute the program from the address indicated by the obtained address information.
    Type: Application
    Filed: November 30, 2010
    Publication date: June 2, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Kohei AIDA
  • Patent number: 7947415
    Abstract: A main object of the invention is to provide a reflective mask for EUV lithography, which may detect an alignment mark by transmission. The invention achieves the object by providing a reflective mask comprising a substrate, a multilayer formed on one side of the substrate, an intermediate layer formed on the multilayer, an absorber formed in pattern on the substrate on which the multilayer and the intermediate layer are formed, and a conductive layer formed on the other side of the substrate, wherein the pattern of the absorber constitutes a circuit pattern and an alignment mark, and in an alignment region where the alignment mark is provided, the other side of the substrate is exposed.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: May 24, 2011
    Assignees: Dai Nippon Printing Co., Ltd., NEC Electronics Corporation
    Inventors: Tsuyoshi Amano, Hiroyuki Shigemura
  • Patent number: 7944411
    Abstract: To equalize the intensity of light emitted by display elements on a display device, a plurality of current-drive circuits are connected in cascade through two terminals of each of the current-drive circuits, each comprising a reference current generation section including a reference resistor and a plurality of current drive sections. Reference current sunk by an external reference current source causes a voltage drop across the reference resistor, and the voltage drop is applied across a current adjustment resistor In response to an image signal, the current-drive circuit outputs current, determined by multiplying each of a plurality of internal reference currents by an optional factor and summing the resulting currents to the display elements. Since the magnitude of the internal reference current flowing inside the current-drive circuit can be varied by varying the value of the current adjustment resistor, gamma correction can be applied to drive current with high accuracy.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: May 17, 2011
    Assignee: NEC Electronics
    Inventor: Yutaka Saeki
  • Patent number: 7923843
    Abstract: Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plug 9c which is formed into a beaded shape in a layer underlying two interconnects 11C and 11D and which also electrically connects the two interconnects 11C and 11D is included. The two interconnects 11C and 11D are separated to each other and are formed in a same layer. The contact plug 9c is simultaneously formed with a contact plug 9b to be connected to an interconnect 4b and a contact plug 9a to be connected to a source/drain region 6.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: April 12, 2011
    Assignee: NEC Electronics Corporation
    Inventors: Michihiro Kobayashi, Hirofumi Nikaido, Nobuyuki Katsuki, Yasuhiro Kawakatsu