Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.

Abstract: A structure for picking up a collector region including a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, wherein a depth of the doped polysilicon layer is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the isolation regions.

Abstract: A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process.

Abstract: A structure for picking up a collector region is disclosed. The structure includes a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: a first polysilicon layer located below the isolation regions, and a second polysilicon layer located on and in contact with the first polysilicon layer, the first polysilicon layer being doped with a dopant having a higher diffusivity or higher concentration than a dopant of the second polysilicon layer, wherein a depth of the polysilicon stacks is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the second polysilicon layer; and the depth of the second polysilicon layer is greater than a depth of the isolation regions.

Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

Abstract: A superjunction device in which corner portions of each annular-shaped second trench are composed of a plurality of alternately arranged first sides and second sides. The first sides are parallel to a plurality of parallel arranged first trenches in a current-flowing area, while the second sides are perpendicular to the first sides and the first trenches. Such design ensures that Miller indices of sidewalls and bottom face of any portion of each second trench belong to the same family of crystal planes. Moreover, with this design, the corner portions of the second trenches can be filled with a silicon epitaxial material at the same rate with the rest portions thereof, which ensures for the second trenches to be uniformly and completely filled without any defects in the corner portions and hence improve the performance of the superjunction device.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies.

Abstract: The present invention discloses an LDMOS device structure, including a MOS transistor cell, wherein an isolation region is formed on each outer side of both a source region and a drain region of the MOS transistor cell; each isolation region includes a plurality of isolation trenches and isolates the MOS transistor cell from its surroundings; the height of the isolation region is smaller than that of a gate of the MOS transistor cell. The present invention also discloses a manufacturing method of the LDMOS device structure, including forming isolation trenches by lithography and etching processes, then forming isolation regions of SiO2 by depleting silicon between isolation trenches through high-temperature drive-in. The present invention can reduce parasitic capacitance, surface unevenness and difficulty of subsequent process and realize the production of small-size gate devices by forming a thicker field oxide layer and a gap structure of isolation trenches.

Abstract: A digital correction circuit for a pipelined analog-to-digital converter (ADC) is disclosed. Compared to the conventional digital correction circuit which uses adders to perform operations in ADC digital correction part and hence needs a rather long operation time, the digital correction circuit of this invention can reduce the time needed in operations in the finial digital correction circuits and thus can optimize operation time, by allocating the operations to a plurality of pipeline stages of second sub-circuits configured to synchronize digital codes, each of which can perform part of the operations only with NAND gates, NOR gates, phase inverters and D-type flip-flops, without needing to use adders.

Abstract: A terminal structure for superjunction device is disclosed. The terminal structure comprises from inside out at least one P type implantation ring and several P type trench rings formed in an N type epitaxial layer to form alternating P type and N type regions. A channel cut-off ring is formed at the border of the device. The P type implantation ring is formed adjacent to the active area of the device and covers at least one trench ring. A terminal dielectric layer is formed to cover the P type implantation ring and the trench rings. A plurality of field plates are formed above the terminal dielectric layer. Methods of manufacturing terminal structure are also disclosed.

Abstract: An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.

Abstract: A field stop structure is disclosed. The field stop structure is divided into a three-dimensional structure by a plurality of trenches formed on a back side of a silicon substrate and hence obtains a greater formation depth in the substrate and can achieve a higher ion activation efficiency. Moreover, a first electrode region of a fast recovered diode (FRD) is formed in the trenches, thereby enabling the integration of a FRD with an insulated gate bipolar transistor (IGBT) device. Methods for forming field stop structure and reverse conducting IGBT semiconductor device are also disclosed.

Abstract: A differential amplifier has first and second input terminals (T1, T2), an output terminal, a differential stage connected to the first and second input terminals, and an amplification stage having an input terminal thereof connected to an output terminal of the differential stage and an output terminal thereof connected to the output terminal. The differential stage includes a first differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the output terminal, a second differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the second input terminal (T2), a first current source for supplying current to the first differential pair, a second current source for supplying current to the second differential pair, and a load circuit connected to the output pairs of the first and second differential pairs.

Abstract: A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues.

Abstract: A PN-junction varactor in a BiCMOS process is disclosed which comprises an N-type region, a P-type region and N-type pseudo buried layers. Both of the N-type and P-type regions are formed in an active area and contact with each other, forming a PN-junction; the P-type region is situated on top of the N-type region. The N-type pseudo buried layers are formed at bottom of shallow trench field oxide regions on both sides of the active area and contact with the N-type region; deep hole contacts are formed on top of the N-type pseudo buried layers in the shallow trench field oxide regions to pick up the N-type region. A manufacturing method of PN-junction varactor in a BiCMOS process is also disclosed.

Abstract: A method of preventing dopant from diffusing into atmosphere in a BiCMOS process is disclosed. The BiCMOS process includes the steps of: depositing a first silicon oxide layer and a silicon nitride layer over surface of a silicon substrate; etching the silicon substrate to form a plurality of shallow trenches therein; depositing a second silicon oxide layer over surface of the silicon substrate and forming silicon oxide sidewalls over inner side faces of each of the plurality of shallow trenches; forming a heavily doped pseudo buried layer under a bottom of one of the plurality of shallow trenches by implanting a dopant with a high concentration; performing an annealing process to promote diffusion of the dopant contained in the pseudo buried layer, wherein the method includes growing, by thermal oxidation, a silicon oxide layer over a bottom of each of the plurality of shallow trenches during the annealing process.

Abstract: A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed.

Abstract: A parasitic PIN device in a BiCMOS process is disclosed. The device is formed on a silicon substrate, in which an active region is isolated by shallow trenches. The device includes: an N-type region, consisting of N-type pseudo buried layers respectively formed at the bottom of shallow trench isolation oxide layers and extending into the active region; an I-type region, consisting of an N-type collector implantation region formed in the active region and contacting with the N-type region; a P-type region, consisting of a P-doped intrinsic base epitaxial layer on a surface of the active region and contacting with the I-type region. The device of the present invention has a low insertion loss and a high isolation. A manufacturing method of parasitic PIN device in compatible with existing BiCMOS process is also disclosed.

Abstract: A method of double-sided patterning including positioning a first silicon wafer with its back side facing upwards and forming one or more deep trenches serving as alignment marks on the back side of the first silicon wafer; performing alignment with respect to the alignment marks and forming a back-side pattern on the first silicon wafer; depositing a polishing stop layer on the back side of the first silicon wafer; flipping over the first silicon wafer and bonding its back side with the front side of a second silicon wafer; polishing the front side of the first silicon wafer to expose the alignment marks from the front side; performing alignment with respect to the alignment marks and forming a front-side pattern on the first silicon wafer; removing the second silicon wafer and the polishing stop layer to obtain a double-sided patterned structure on the first silicon wafer.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed.