Patents Assigned to NEC Electronics
  • Publication number: 20100327403
    Abstract: One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides.
    Type: Application
    Filed: May 19, 2010
    Publication date: December 30, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Masafumi Yamaji
  • Publication number: 20100327951
    Abstract: A semiconductor integrated circuit includes a first circuit, a second circuit and a control circuit. The first circuit is configured by a first MOS transistor, and a threshold voltage of the first MOS transistor is a first threshold voltage. The second circuit has same logic as the first circuit, and is configured by a second MOS transistor. A threshold voltage of the second MOS transistor is a second threshold voltage, and the second threshold voltage is lower than the first threshold voltage. The control circuit makes one of the first circuit and the second circuit operate depending on a temperature of a chip. The first circuit and the second circuit are installed in a chip.
    Type: Application
    Filed: April 29, 2010
    Publication date: December 30, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Atsuhisa Fukuoka
  • Patent number: 7860148
    Abstract: A receiving circuit which receives information using a multi-carrier signal comprises a phase rotation amount calculator which calculates a phase rotation amount of a multi-carrier signal included in a first frequency band according to a pilot-sub carrier included in the first frequency band, a converter which calculates a phase rotation amount of a multi-carrier signal included in a second frequency band according to the phase rotation amount of the multi carrier signal included in the first frequency band.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: December 28, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takahiro Sato
  • Patent number: 7859509
    Abstract: In a semiconductor integrated circuit device, a shift register includes a plurality of cascaded flip-flops adapted to generate shift pulse signals in response to a start signal. A logic circuit receives a pulse signal at its input end and supplies the pulse signal from its plurality of output ends to the flip-flops. The pulse signal at each of the plurality of output ends is allowed and prohibited by a corresponding one of the shift pulse signals.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: December 28, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Toshiaki Ueda
  • Patent number: 7859504
    Abstract: A liquid crystal display device according to an embodiment of the present invention includes an active matrix type liquid crystal display panel, in which a set value of a common voltage applied to a common electrode of the liquid crystal display panel is determined based on input image data, and a timing of changing the common voltage to the preset value in accordance with a timing of driving at least one of a scan line and a signal line of the liquid crystal display panel.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: December 28, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hirobumi Furihata, Takashi Nose
  • Publication number: 20100320539
    Abstract: A semiconductor device has an SOI (Silicon On Insulator) structure and comprising a P-channel FET and an N-channel FET which are formed on an insulating film. The semiconductor device includes: at least two of first, second, third and fourth PN-junction elements. The first PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of source/drain regions of the P-channel FET and the N-channel FET, respectively. The second PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the source/drain region and a channel region in the P-channel FET, respectively. The third PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of a channel region and the source/drain region in the N-channel FET, respectively.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 23, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Hiroshi Furuta
  • Publication number: 20100320521
    Abstract: A semiconductor device according to an exemplary embodiment of the present invention includes a memory cell including an information storage portion including a capacitor upper electrode of a DRAM cell and a capacitor lower electrode formed below the upper electrode and an access transistor for controlling access to the information storage portion, a bit-line connected to the access transistor to write or read data to or from the information storage portion, a word line connected to a gate electrode of the access transistor to control the access transistor, and a capacitive element including an upper electrode made from a same layer as a first metal line formed above the capacitor upper electrode and a lower electrode made from a same layer as the capacitor upper electrode, the capacitive element being formed outside an area where the memory cell is formed.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 23, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Katsuya Izumi
  • Patent number: 7855537
    Abstract: A voltage supply circuit includes an output transistor causing a first current to flow to an output terminal of the voltage supply circuit based on a control voltage applied from an error amplifier to a control terminal of the output transistor; and an overcurrent protection circuit including a reference transistor causing a second current to flow to the output terminal, the second current having an amount corresponding to an amount of the first current, the overcurrent protection circuit regulating a level of the control voltage based on comparison between a detection voltage caused based on the second current and a reference voltage.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: December 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroki Aizawa
  • Patent number: 7856103
    Abstract: A microcontroller includes a program memory configured to store a program group and a first encryption key; a CPU; and an identification (ID) storage section configured to store an identification data peculiar to a user of the microcontroller. The CPU executes the program group to generate a second encryption key based on the identification data and the first encryption key and to encrypt a random number with the second encryption key.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: December 21, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Toshio Kimura, Naofumi Ozawa
  • Patent number: 7855532
    Abstract: A power supply circuit includes a first power supply configured to output a first voltage; a second power supply provided separately from the first power supply to output a second voltage; and a boosting circuit configured to use the first voltage as an input voltage to boost the input voltage toward a target voltage. The target voltage has a voltage width, and when an output voltage of the boosting circuit exceeds an upper limit of the target voltage, the input voltage is switched the first voltage of the first power supply to the second voltage of the second power supply.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: December 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hirofumi Fujiwara
  • Patent number: 7855561
    Abstract: A test circuit according to the present invention includes: a synthesis circuit that synthesizes a first test result signal output from a first test target circuit in response to a test instruction, and a second test result signal output from a second test target circuit in response to the test instruction; an inter-block delay generation circuit that delays the second test result signal with respect to the first test result signal; and a test result holding circuit that holds a synthesized test result signal every predetermined timing, the synthesized test result signal being output from the synthesis circuit.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: December 21, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kenichi Itoh
  • Publication number: 20100318706
    Abstract: Provided is a bus arbitration circuit including: a fixed priority determination circuit that grants a bus use right to an access request from a higher priority bus master among access requests from a plurality of bus masters; and a determination adjustment circuit that determines whether or not to assert the access request from the plurality of bus masters to the fixed priority determination circuit. The determination adjustment circuit masks an access request from a bus master which is granted the bus use right, for a given period of time, when the access request from the bus master which is granted the bus use right and an access request from a bus master which is not granted the bus use right compete with each other.
    Type: Application
    Filed: May 12, 2010
    Publication date: December 16, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Kazuyuki KOBAYASHI
  • Publication number: 20100314749
    Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.
    Type: Application
    Filed: August 4, 2010
    Publication date: December 16, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Yoichiro KURITA
  • Publication number: 20100314777
    Abstract: A semiconductor device includes: a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; an interconnect (second interconnect trench) composed of a metallic film provided in an interconnect trench (second copper interconnect) and a plug composed of a metallic film provided in a connection hole (via hole) coupled to the second interconnect trench, both of which are provided in the interlayer insulating film; a first sidewall provided on a side surface of the via hole; and a second sidewall provided on a side surface of the second interconnect trench, and a thickness of the first sidewall in vicinity of a bottom of the side surface of the via hole is larger than a thickness of the second sidewall in vicinity of a bottom of the second interconnect trench.
    Type: Application
    Filed: May 3, 2010
    Publication date: December 16, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Noriaki Oda
  • Publication number: 20100314773
    Abstract: A semiconductor device has: a radiator plate that is maintained at a predetermined potential; an SOI (Silicon On Insulator) chip mounted on the radiator plate; and thermal grease applied to an interface between the radiator plate and the SOI chip. The SOI chip has: a first silicon substrate forming a circuit element part; a second silicon substrate facing the radiator plate; and an insulating film formed between the first silicon substrate and the second silicon substrate. The first silicon substrate and the second silicon substrate are electrically connected to each other. The thermal grease is conductive and electrically connects the second silicon substrate and the radiator plate.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 16, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Nobuyuki Kobayashi
  • Publication number: 20100316338
    Abstract: An optical communication module includes a CAN member including a conductive stem member where an optical electronic device is mounted and a conducive lens cap that holds an optical lens optically coupled with the optical electronic device, is connected to the stem member in a conductive state, and covers a surrounding portion of the optical electronic device; a conductive cylindrical holder which is disposed around the lens cap, is fixed to the CAN member in an insulation state through an insulating resin, and is provided with an opening facing the optical lens; and an optical receptacle including an optical member that is optically coupled with the optical lens and the optical electronic device through the opening and a holding frame that holds the optical member inside.
    Type: Application
    Filed: April 28, 2010
    Publication date: December 16, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Atsushi SHONO
  • Publication number: 20100314727
    Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.
    Type: Application
    Filed: May 20, 2010
    Publication date: December 16, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Shinichi Uchida, Takasuke Hashimoto, Masayuki Furumiya, Kimio Hosoki, Hideo Ohba
  • Publication number: 20100315172
    Abstract: A spread spectrum clock generator includes a voltage-controlled oscillator generating an operation clock, a feedback control unit, a modulated pulse generation unit generating a pulse signal obtained by performing a delta-sigma modulation on a component fluctuating a frequency of the operation clock, a level set unit setting an amplitude of the pulse signal, an adder adding a voltage generated by the feedback control unit and the pulse signal whose amplitude is set by the level set unit, and a low pass filter filtering a signal outputted from the adder and generating a control voltage applied to the voltage-controlled oscillator. The feedback control unit compares a phase of the operation clock with a phase of a reference clock, and based on results of the comparison, generates a voltage used as a reference to oscillate the voltage-controlled oscillator.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 16, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Yoshinori Kanda
  • Publication number: 20100317200
    Abstract: A method of manufacturing a semiconductor device includes performing heat treatment for activating impurities of a transistor having a gate electrode over a gate insulating film with a higher relative permittivity than a silicon oxynitride film or a silicon oxide film. In the heat treatment, a first heat treatment, in which a wafer surface is heated at a temperature of 800 to 1000° C. in 5 to 50 milliseconds by low-output flash lamp annealing or laser annealing, and a second heat treatment, in which the wafer surface is heated at a temperature equal to or more than of 1100° C. in 0.1 to 10 milliseconds by flash lamp annealing or laser annealing with a higher output than in the first heat treatment, are performed in this order.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 16, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Takashi Onizawa
  • Patent number: 7852704
    Abstract: A semiconductor storage device according to one aspect of the present invention includes a DRAM cell including one transistor and one capacitor, in which one of a first voltage and a second voltage is applied to a gate of the transistor, the first voltage being a selected voltage, and the second voltage being a non-selected voltage, a voltage difference between the first voltage and the second voltage is larger than a voltage difference between a power supply voltage and a ground voltage, and one of the ground voltage and the power supply voltage which is closer to the non-selected voltage is applied to a back gate of the transistor irrespective of selection or non-selection.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: December 14, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroyuki Takahashi, Atsushi Nakagawa