Patents Assigned to NEC Electronics
  • Publication number: 20110050197
    Abstract: A reference current or voltage generation circuit which forms a self feedback circuit with a plurality of transistors and generates a reference current or a reference voltage, the reference current or voltage generation circuit including a normally-on type transistor that has a gate connected to a first power supply and is connected between a node and a second power supply. Moreover, a voltage of the node is substantially equal to a voltage of the first power supply when the reference current or voltage generation circuit does not operate, and the voltage of the node fluctuates from the voltage of the first power supply toward a voltage of the second power supply by a predetermined value or more when the reference current or voltage generation circuit operates.
    Type: Application
    Filed: July 20, 2010
    Publication date: March 3, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Tachio Yuasa
  • Publication number: 20110050342
    Abstract: A push-pull amplifier including first to third current paths. The first current path includes first transistor allowing first current to flow through the first current path according to input signal. The second current path includes second transistor allowing second current having opposite phase to the first current to flow through the second current path according to the first current; first resistor; and third transistor connected to one end of the first resistor and having control terminal connected to the other end of the first resistor. The third current path includes output terminal; fourth transistor allowing current having the same phase as the first current to flow through the third current path according to the input signal; and fifth transistor allowing current having the same phase as the second current to flow through the third current path according to voltage of first node between the first resistor and the third transistor.
    Type: Application
    Filed: July 21, 2010
    Publication date: March 3, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Tachio Yuasa
  • Publication number: 20110050327
    Abstract: Provided is a semiconductor device including: a first charge pump circuit that generates a first control signal based on electric charge of a first pumping capacitor accumulated through a first drive transistor; a second charge pump circuit that generates a second control signal based on electric charge of a second pumping capacitor accumulated through a second drive transistor; a third charge pump circuit that transfers electric charge between an output terminal and a reference voltage terminal through a third drive transistor; and a fourth charge pump circuit that transfers electric charge between the output terminal and the reference voltage terminal through a fourth drive transistor. Conductive states of the first and third drive transistors are controlled based on the second control signal, and conductive states of the second and fourth drive transistors are controlled based on the first control signal.
    Type: Application
    Filed: June 28, 2010
    Publication date: March 3, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Kenji Fujitani
  • Publication number: 20110051541
    Abstract: A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal.
    Type: Application
    Filed: June 18, 2010
    Publication date: March 3, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Akihiro Banno
  • Publication number: 20110050983
    Abstract: An exemplary embodiment of the present invention is an autofocus method that includes moving a focus lens according to an image signal generated from an image of a subject formed by an imaging optical system with a focus lens, obtaining a focus contrast of each of multiple image signals generated in a case of moving a position of the focus lens; and determining a moving direction of the focus lens according to the multiple obtained focus contrasts in response to a focus instruction.
    Type: Application
    Filed: June 18, 2010
    Publication date: March 3, 2011
    Applicant: NEC Electronics Corporation
    Inventors: Hiromi Takeda, Takeshi Ohtsuki
  • Publication number: 20110050761
    Abstract: A display device uses a plurality of pixel circuits each of which includes a light-emitting element; a light-emission control switching element; a current control circuit for supplying a driving current, which corresponds to gray-level display data, to the light-emitting element via the light-emission control switching element; and a voltage control circuit, which includes a first capacitance element for storing a voltage corresponding to the gray-level display data, and controls ON/OFF operation of the light-emission switching element in accordance with the voltage stored. If the gray-level display data is data for causing the light-emitting element to display less than a certain luminance, the current control circuit supplies the light-emitting element with a constant driving current corresponding to the gray-level display data for displaying the certain luminance, and the voltage control circuit controls the ON time of the light-emission control switching element in accordance with a voltage stored.
    Type: Application
    Filed: July 20, 2010
    Publication date: March 3, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Teru YONEYAMA
  • Publication number: 20110044007
    Abstract: A heat sink 109 is configured by a plate component having a combined structure composed of a recess and a projection formed thereon, wherein the recess is formed by allowing a part of the plate component to be set back from the surface level of the residual region, and the projection is formed on one surface of the plate component with the progress of formation of the recess, so as to be built up above the level of the residual region of the one surface.
    Type: Application
    Filed: July 19, 2010
    Publication date: February 24, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Harumi Mizunashi
  • Publication number: 20110042802
    Abstract: A semiconductor device includes an electrode pad and an external connection terminal. The external connection terminal contains Sn equal to or more than 50 wt %, Sn and Pb equal to or more than 90 wt % in total, or Pb equal to or more than 85 wt %, and the surface thereof is coated with an Au layer. The thickness of the Au layer is preferably equal to or more than 10 nm and equal to or less than 1 ?m. The weight of the Au layer is preferably equal to or less than 0.6% of the weight of the external connection terminal.
    Type: Application
    Filed: July 19, 2010
    Publication date: February 24, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Fumiyoshi Kawashiro
  • Publication number: 20110043262
    Abstract: An input interface circuit according to the present invention includes an input first stage circuit that is connected to a signal terminal, where the signal terminal receives external data, and a phase adjustment circuit that adjusts an external input clock and a latch timing signal to be in phase, where the latch timing signal is output to latch circuits included in the input first stage circuit. The phase adjustment circuit adjusts delay time of the latch timing signal that passes through the clock tree circuit and is supplied to the latch circuit in response to a comparison result between the clock and an output from a replica delay circuit which is replicated from the clock.
    Type: Application
    Filed: June 10, 2010
    Publication date: February 24, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Kazuo Watanabe
  • Publication number: 20110038979
    Abstract: A die unit that maintains uniform quality of a work despite continuous operation is provided. The die unit includes a lower die holder including a base hole, an upper die holder including a through hole, a pillar having an end portion inserted to the base hole and the other end portion slidably inserted through the through hole, so as to allow the upper die holder to slide toward and away from the lower die holder, an annular bushing attached to the through hole so as to slide along the pillar, and a die element and a punch attached to one of the lower die holder and the upper die holder respectively. A spacer is provided at least one of between an inner circumferential surface of the through hole and the bushing, and between an inner circumferential surface of the base hole and the pillar, and the spacer has lower thermal conductivity than the upper die holder or the lower die holder on which the spacer is provided.
    Type: Application
    Filed: July 19, 2010
    Publication date: February 17, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Tooru Kumamoto
  • Publication number: 20110032014
    Abstract: A multiplier PLL multiplies a reference clock and outputs the multiplied clock. A DLL compares the clock output from the multiplier PLL with a clock obtained by delaying the clock output from the multiplier PLL. The DLL generates a delay signal having a given amount of delay based on the comparison result. A delay control signal operation circuit generates a delay control signal based on the delay signal generated by the DLL. A first delay circuit delays an input signal based on the delay control signal generated by the delay control signal operation circuit.
    Type: Application
    Filed: June 30, 2010
    Publication date: February 10, 2011
    Applicant: NEC Electronics Corporation
    Inventors: Masahiko Shihara, Atsushi Tangoda
  • Publication number: 20110032004
    Abstract: A light-receiving circuit includes a photodiode that converts an input optical signal to a current signal; a current-voltage converting circuit that outputs an output voltage signal obtained by adding a reference voltage to a voltage signal proportional to the current value of the current signal; and an input current limiting unit that supplies the current-voltage converting circuit with the current signal upon limiting the current value of this current signal based upon the reference voltage in such a manner that the output voltage signal will not exceed a constant value irrespective of the value of the reference voltage.
    Type: Application
    Filed: July 8, 2010
    Publication date: February 10, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Hitoshi Imai
  • Publication number: 20110032135
    Abstract: A D-A converter includes a resistor string that generates a plurality of voltages including an upper limit voltage, a lower limit voltage, and an intermediate voltage, a first selector that selects and outputs a first voltage among the plurality of voltages according to a lower bit, the first voltage being selected from the intermediate voltage and a voltage lower than the intermediate voltage, a second selector that selects and outputs a second voltage according to a higher bit, the second voltage being one of a lower power supply voltage and the intermediate voltage or a voltage higher than the intermediate voltage, a third selector that selects and outputs a third voltage according to the higher bit, the third voltage being selected from the lower limit voltage and the lower power supply voltage; and an amplifier that adds the first voltage and the second voltage and subtracts the third voltage.
    Type: Application
    Filed: June 30, 2010
    Publication date: February 10, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Fumio Tonomura
  • Publication number: 20110027987
    Abstract: A method for manufacturing a semiconductor device includes forming a laminated structure of a plurality of metal films on a semiconductor substrate using an electroless plating method. The forming of the metal films includes: performing an electroless plating process including a reduction reaction using a first plating tank; and performing an electroless plating process by only a substitution reaction using a second plating tank. The electroless plating process including the reduction reaction that is performed using the first plating tank is performed in a shading environment, and the electroless plating process performed by only the substitution reaction using the second plating tank is performed in a non-shading environment.
    Type: Application
    Filed: June 9, 2010
    Publication date: February 3, 2011
    Applicant: NEC Electronics Corporation
    Inventors: Nobuaki Takahashi, Masahiro Komuro
  • Publication number: 20110024865
    Abstract: According to an exemplary aspect of the present invention, at least a semiconductor mesa and a semiconductor layer covering at least the side wall of the mesa and a semiconductor mesa are formed on an n-type semiconductor substrate. The semiconductor mesa includes at least a light absorption layer and a p-type contact layer. The principal surface of the semiconductor substrate tilts at an angle ? to the (100) plane. The angle ? is 0.1 degree?|?|?10 degrees.
    Type: Application
    Filed: June 29, 2010
    Publication date: February 3, 2011
    Applicant: NEC ELectronics Corporation
    Inventors: Takashi MATSUMOTO, Isao WATANABE, Tomoaki KOI
  • Publication number: 20110024863
    Abstract: A mesa photodiode which includes a mesa, the side wall of the mesa (a light-receiving region mesa) and at least a shoulder portion of the mesa in an upper face of the mesa are continuously covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type (an undoped InP layer, for example) that is grown on the side wall and the upper face of the mesa. In the semiconductor layer, a layer thickness D1 of a portion covering the side wall of the mesa is equal to or greater than 850 nm.
    Type: Application
    Filed: June 8, 2010
    Publication date: February 3, 2011
    Applicant: NEC Electronics Corporation
    Inventors: Tomoaki Koi, Isao Watanabe, Takashi Matsumoto
  • Publication number: 20110024832
    Abstract: A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions.
    Type: Application
    Filed: October 12, 2010
    Publication date: February 3, 2011
    Applicant: NEC Electronics Corporation
    Inventors: Kinya Ohtani, Kenya Kobayashi
  • Publication number: 20110025416
    Abstract: A differential amplifier including: 1st transistor that is connected between 1st power-supply terminal and 1st output terminal, and has a control terminal receiving one of the differential input signals; 2nd transistor that is connected between 2nd power-supply terminal and 1st output terminal, and has a control terminal receiving the other of the differential input signals; 1st switch that is connected between 1st power-supply terminal and 1st transistor; 3rd transistor that is connected between 2nd power-supply terminal and 2nd output terminal, and has a control terminal is input to one of the differential input signals; 4th transistor that is connected between 1st power-supply terminal and 2nd output terminal, and has a control terminal receiving the other of the differential input signals; 2nd switch that is connected between 2nd power-supply terminal and 3rd transistor. Drive state of 1st and 2nd switches are controlled by a control signal.
    Type: Application
    Filed: June 2, 2010
    Publication date: February 3, 2011
    Applicant: NEC Electronics Corporation
    Inventors: Michimasa Yamaguchi, Kenichi Kawakami
  • Publication number: 20110018137
    Abstract: A plurality of projections, respectively given later as cores of a plurality of external connection terminals, are formed first by selectively forming a curable resin layer over a protective insulating film; flat portions are then formed respectively on the top surfaces of the plurality of projections, by pressing a molding jig having a flat opposing surface onto the top surfaces of the plurality of projections, before the projections are cured; the plurality of projections are cured; and the plurality of external connection terminals, and the plurality of interconnects are formed, by selectively forming an electro-conductive film over the plurality of projections, the protective insulating film, and the plurality of electrode pads.
    Type: Application
    Filed: June 4, 2010
    Publication date: January 27, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Fumihiro Bekku
  • Publication number: 20110019379
    Abstract: A printed wiring board includes a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of all lands, wherein a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area.
    Type: Application
    Filed: June 28, 2010
    Publication date: January 27, 2011
    Applicant: NEC Electronics Corporation
    Inventor: Koujirou Shibuya