Abstract: A semiconductor integrated circuit device includes: a first power supply region, power supply to which is controlled; and a second power supply region connected with a first power supply region. The first power supply region includes: a floating preventing circuit configured to fix an output voltage from the first power supply region to the second power supply region to a ground voltage in synchronization with stop of power supply.

Abstract: A local signal generation circuit in accordance with one aspect of the present invention includes a phase comparator that detects a phase difference between a reference signal and a feedback signal and outputs a error signal, a charge-pump circuit that receives the error signal and generates a step-up voltage, a loop filter that generates a tuning voltage by changing the shape of the step-up voltage, a voltage control oscillator that generates a first output signal having a predefined frequency based on the tuning voltage, and a prescaler that outputs a second output signal generated by dividing the frequency of the first output signal to a predefined frequency and also outputs a frequency-division signal generated by dividing the frequency of the first output signal to the predefined frequency to a frequency divider that generates the feedback signal.

Abstract: A system including sub-networks mounted with different kinds of protocols/profiles, a gate way/proxy for connecting the sub-networks, and nodes on the sub-networks, the gateway/proxy being mounted with processing of a physical layer and a data link layer as a protocol of the sub-network and having a common transport layer and a service proxy and a client proxy shared by the sub-networks.

Abstract: A printer includes a printing part that prints inputted printing information on paper while moving by gravity and supports that support the printing part and the printing medium facing each other so that the printing part is movable in the gravity direction. The printing part corrects the inputted printing information according to a moving distance and a moving speed of the printing part and prints corrected printing information on the printing medium.

Abstract: A reference voltage generator according to an embodiment of the present invention includes: a voltage setting circuit generating a first voltage having a predetermined voltage difference from an output voltage; a voltage buffer receiving the first voltage and outputting a first power supply substantially equal to the first voltage; a voltage clamp circuit operating based on a second power supply and a third power supply; and a band-gap circuit generating the output voltage, the band-gap circuit operating based on the second power supply and the first power supply output from the voltage clamp circuit.

Abstract: An amplifier in an embodiment of the present invention has MOS transistors connected serially between a power supply VDD and a ground terminal GND; an output terminal Vout connected to a node provided between the MOS transistors; a first mirror capacity provided between the gate of a MOS transistor and the output terminal Vout; and a second mirror capacity provided between the gate of another MOS transistor and the output terminal Vout. The amplifier further includes a first switching circuit for connecting one end of the first mirror capacity to the power supply terminal VDD or to the gate of a MOS transistor; and a second switching circuit for connecting one end of the second mirror capacity to the ground terminal GND or to the gate of another MOS transistor.

Abstract: An output circuit includes a differential section configured to amplify an inputted differential signal; a current source section configured to supply a current to the differential section; a load resistance section connected with the differential section; and a control unit configured to set a value of the current from the current source section and a resistance value of the load resistance section based on a signal supplied to the control unit. The output circuit converts the differential signal into an output signal of a different interface level from that of the differential signal and balance-transmits the output signal.

Abstract: A photomask is to be used for exposure of a semiconductor wafer with the dipole illumination light, and includes a main opening, a first assist opening, a second assist opening, a third assist opening and a fourth assist opening. Each of the assist openings is located so that the central point thereof is deviated from both of a first straight line parallel to a first direction and passing the central point of the main opening, and a second straight line parallel to a second direction and passing the central point of the main opening. Here, the first direction is the direction among in-plane directions of the photomask that is parallel to an alignment direction of an effective light source distribution of the dipole illumination light. Also, the second direction is the direction among in-plane directions of the photomask that is perpendicular to the alignment direction.

Abstract: A fuse cutting test method to test the state of a fuse includes measuring the current flowing through the fuse and determining the fuse to be either broken, or not broken, or in a state therebetween, based on the measured current.

Abstract: A semiconductor device wherein an electrode pad to be contacted a test probe for performing probe testing, a bonding area mark for defining a bonding area which performs wire boding on the electrode pad, and a probe area mark for defining a probe repair area for repairing or replacing the test probe for the electrode pad.

Abstract: A power noise cycle is obtained from a dynamic IR drop analysis and a delay of a delay pass is a multiple of the noise cycle. Thereby, a delay increment and a delay decrement of a power noise amount (delay time×power noise amplitude) received when an internal signal of the semiconductor integrated circuit passes through a delay pass circuit are approximately the same.

Abstract: A receiver circuit is provided with: a plurality of input terminals; a plurality of hold circuits holding reception signals received by the plurality of input terminals; a detector circuit detecting clock bits from selected one of the reception signals to recover a clock signal in response to the detected clock bits; and a clock circuit connected to the detector circuit and generating one or more internal clock signals from the clock signal. The hold circuits commonly receive the internal clock signal(s) and perform sampling of the reception signals commonly in synchronization with the internal clock signal(s).

Abstract: There is provided a method and an apparatus for manufacturing a semiconductor device having a lidless and highly reliable flip-chip structure. The method for manufacturing a semiconductor device wherein an underfill resin is filled in a space between a substrate and a semiconductor chip includes injecting a first underfill resin in said space under a first injecting condition; specifying a location where the fillet height of the underfill resin formed on the side of said semiconductor chip does not meet a prescribed standard; and injecting a second underfill resin in a location where the fillet height does not meet the prescribed standard under a second injecting condition. Since the fillet heights can uniformly meet the prescribed standard, the concentration of stress can be avoided, and a semiconductor device having a lidless and highly reliable flip-chip structure can be manufactured.

Abstract: A phase determination unit in a signal processing circuit generates sampling clocks with different phases in a clock generator and sequentially provides them to an analog-to-digital convertor. Then, the phase determination unit obtains differences between each adjacent two signal levels in each sampled digital signal by use of the sampling clocks, and monitors a polarity change in the differences, extracts a more inappropriate phase for use in sampling from phases of the sampling clocks on the basis of the absolute values of the differences where the polarity change is detected, and determines an antiphase of the extracted phase as a phase of the sampling clock to be provided to the analog-to-digital convertor.

Abstract: A standard cell includes an input terminal, an output terminal, first and second inverters coupled in series between the input and output terminals, the first inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor being coupled between a first power source terminal and a first node, and the second transistor being coupled between a second node and a second power source terminal, and a plurality of resistance elements which are used to provide a conductivity path between the first and second nodes, in order to adjust a duty ratio of a signal which passes the standard cell.

Abstract: A plasma processing apparatus is provided which can suppress variation in the electrode impedance varying due to a product or the like attached in a processing chamber, and which prevents variation in electric power consumed for plasma. According to the present invention, a plasma processing apparatus comprises a radiofrequency power supply 5 outputting radiofrequency power with reference to GND; a switching device 24 connected to the radiofrequency power supply; a lower electrode 2 connected to the switching device 24; an impedance control device 22 connected between the lower electrode 2 and GND; an impedance measuring device 23 connected between the switching device 24 and GND; and a controller 26 controlling the impedance control device 22 according to the value of impedance (the electrode impedance) measured by the impedance measuring device 23.

Abstract: Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level.

Abstract: A placement and routing processing unit performs placement and routing processing on a customer circuit based on design data. An embedded circuit generation processing unit refers to a library including embedded circuit information, grasps physical positional relationships among elements such as terminals and wires, and checks whether the elements are short-circuited to each other or not. The library including embedded circuit information records a result of placement and routing output by the placement and routing processing unit, attribute information on a test circuit to be embedded into the customer circuit or terminal information and wire position information, and the like on the test circuit. The elements that are short-circuited to each other are incorporated into a netlist to be generated, as the elements constituting one net.

Abstract: A data transfer apparatus is composed of a transmitter and a receiver. The transmitter includes an output buffer developing a differential signal in response to a data signal, and an amplitude controller. The receiver includes an input buffer converting the differential signal into a single-end signal, and an amplitude detector developing a feedback signal in response to the single-end signal. The amplitude controller controls an amplitude of the differential signal in response to the feedback signal.

Abstract: A semiconductor device has a substrate, a first gate electrode, and a second gate electrode. The substrate has an active region surrounded by an isolation region. The first gate electrode is formed on the active region through a gate insulating film. The second gate electrode is formed on the gate insulating film such that the second gate electrode overlaps at least a part of a boundary between the active region and the isolation region. The first gate electrode and the second gate electrode are separated from each other.