Abstract: A data processing device includes a program execution section to supply an operation direction signal to a peripheral device based on an executed program and execute a branch operation in response to a branch direction signal, and a branch wait operation section to receive the branch direction signal and a peripheral device status notification signal indicating whether an operation performed in the peripheral device is being executed. The branch wait operation section outputs an instruction issue stop signal directing waiting of the branch operation to the program execution section if the branch direction signal is input during a period when the peripheral device status notification signal is active indicating that the operation in the peripheral device is being executed.

Abstract: The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions.

Abstract: An exemplary aspect of an embodiment of the present invention is a voltage-current converter converting an input voltage input to an input terminal to a current to output the current, the voltage-current converter including a first current generating circuit including an input transistor having a gate connected to the input terminal and generating an output current according to a current flowing in the input transistor, and a second current generating circuit including a transistor having a gate having a potential different from potential of a source and a drain, the second current generating circuit generating a superimposed current according to the current flowing in the transistor to supply the superimposed current to the input transistor.

Abstract: A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first conductivity type formed in the semiconductor substrate, a second impurity layer of a second conductivity type formed on the first impurity layer, a first well of the first conductivity type formed on the second impurity layer and supplied with potential from the first impurity layer via an impurity region of the first conductivity type selectively formed in a part of the second impurity layer, and a second well of the second conductivity type formed on the second impurity layer and supplied with potential from the second impurity layer, wherein the impurity concentrations of the first impurity layer and the impurity region are higher than that of the first well, and the impurity concentration of the second impurity layer is higher than that of the second well.

Abstract: A semiconductor device (100) including: a semiconductor substrate including a semiconductor chip formation region (102); a chip internal circuit (124); a signal transmitting/receiving inductor (114) which transmits/receives a signal to/from an outside in a non-contact manner by electromagnetic induction, and transmits/receives a signal to/from the chip internal circuit (124) through electrical connection to the chip internal circuit (124); and a power receiving inductor (112) which has a diameter provided along an outer edge of the semiconductor chip formation region (102) so as to surround the chip internal circuit (124) and the signal transmitting/receiving inductor (114), receives a power supply signal from the outside in the non-contact manner, and is electrically connected to the chip internal circuit (124). Accordingly, power supply can be sufficiently made in the non-contact manner while limiting an increase in chip size when various signals are transmitted/received in the non-contact manner.

Abstract: A data processing apparatus includes an arithmetic circuit and a peripheral device protection circuit that controls access of the arithmetic circuit to the peripheral devices. The peripheral device protection circuit has a first protection preset value and a second protection preset value set as a protection level higher than that of the first protection preset value. The peripheral device protection circuit includes: a setting selection circuit that generates access permission/denial information by referring to the first protection preset value and the second protection preset value when the arithmetic circuit operates at a first operation authority level, or by referring to the second protection preset value when the arithmetic circuit operates at the second operation authority level. An access protection circuit that determines permission/denial of access to the peripheral devices based on access information output from the arithmetic circuit and the access permission/denial information.

Abstract: A semiconductor device includes a silicon substrate, a capacitor element having a lower electrode, a capacitor dielectric film, a TiN film, and a W film, and an interlayer insulation film covering the end and a portion of the upper surface of the lower electrode and disposed with a concave portion at a position corresponding to the lower electrode. The lower electrode is disposed selectively at the bottom of the concave portion, the upper surface of the lower electrode is exposed from the interlayer insulation film in the region for forming the concave portion, the side wall for the concave portion of the interlayer insulation film situates to the inner side of the lower electrode from the end of the lower electrode, and the capacitor dielectric film is disposed so as to cover the upper surface of the lower electrode and cover the interlayer insulation from the side wall for the concave portion to the upper surface of the interlayer insulation film.

Abstract: A high frequency amplifier is provided with: an input terminal receiving a high frequency signal; an output terminal; a three-terminal active element having a first terminal connected with the input terminal and a second terminal connected with the output terminal; a transmission line; and a capacitive structure. The three-terminal active element outputs an output signal from the output terminal in response to the high frequency signal. The transmission line and the capacitive structure are connected in series between the first and output terminals, and operate together as a series resonance circuit. The transmission line functions as an open stub at a series resonance frequency of the series resonance circuit.

Abstract: A semiconductor integrated circuit device of improved wireability, fewer number of wiring layers and strengthened power supply includes a plurality of power pads placed on a semiconductor chip and a plurality of signal pads placed on the semiconductor chip and configured to have a width less than that of the power pads. The signal pads and the power pads are placed in the uppermost wiring layer among a plurality of wiring layers. Signal wiring connecting I/O cells and signal pads is disposed in the uppermost wiring layer. First power wiring electrically connecting the I/O cells and first power pads is disposed in the uppermost wiring layer. Second power wiring connecting internal circuits and second power pads is disposed in the uppermost wiring layer.

Abstract: A semiconductor memory device includes a plurality of word lines arranged above a semiconductor substrate to extend in a row direction; a plurality of digit lines arranged above the semiconductor substrate to extend in a column direction orthogonal to the row direction; a power supply line arranged in parallel to the plurality of digit lines; a plurality of memory cells formed on the semiconductor substrate at intersections of the plurality of word lines and the plurality of digit lines, each of the plurality of memory cells having a drain region and a source region; and a linear conductive section arranged under the power supply line. The power supply line is connected with the linear conductive section which is connected with the source regions of the plurality of memory cells. The drain regions of each of columns of the plurality of memory cells are connected with one of the plurality of digit lines, and the plurality of word lines function as gates of the plurality of memory cells.

Abstract: A motor control circuit includes: a detector outputting a detection signal in accordance with the motor rpm; a counter counting the number of clocks in accordance with a rotational cycle represented by the detection signal; a controller counting a DC motor based on the count value; and a divider dividing a frequency of a basic clock based on a preset division value to generate a counting clock. The divider generates a counting clock having a frequency corresponding to a rotational cycle, and the counter counts the number of counting clocks.

Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.

Abstract: A phase interpolator receives an input clock signal and varies the phase of an output clock signal in accordance with a phase control signal.

Abstract: A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The method includes: forming a via hole in the interlayer insulating film; forming a resin film plugging the via hole on the interlayer insulating film; etching the resin film exposed outside the via hole off with an etching gas mainly containing an active hydrogen species to form a dummy plug composed of the resin film in the via hole; forming a resist mask having an opening for an interconnect on the dummy plug and on the interlayer insulating film.

Abstract: A temperature detection circuit according to the present invention includes a potential generating part and a temperature detection part. The potential generating part generates a potential according to an environmental temperature, and the temperature detection part detects a temperature based on a detection potential generated in the potential generated part. The temperature detection part is a resistive load type inverter circuit that outputs a detection signal when the generated potential reaches a threshold voltage. The potential generating part applies the detection potential to the inverter circuit through a temperature sensor including cascaded diodes and an NchMOSFET. The threshold voltage of the inverter circuit is determined based on the NchMOSFET in the inverter circuit, and the NchMOSFET is a MOSFET having the same characteristic as the NchMOSFET of the potential generating part.

Abstract: A manufacturing method for manufacturing an electronic device includes a first electronic component and a second electronic component; and a bond part for the first electronic component joined to another bond part for the second electronic component. In a first process of this manufacturing method, the metallic bond part for the first electronic component is placed directly against the metallic bond part for the second electronic component, pressure is applied to the first electronic component and the second electronic component and, after metallically joining the above two bond parts, the pressure applied to the first electronic component and the second electronic component is released. In a second process in the manufacturing method, a clamping member affixes the relative positions of the joined first electronic component and second electronic component, and heats the first electronic component and the second electronic component to maintain a specified temperature.

Abstract: A self-diagnostic circuit includes a setting unit receiving a plurality of detection signals generated in an integrated circuit device, and determining a type of detection signal to be detected among the received plurality of detection signals. A counter is coupled to the setting unit and counts a number of a signal corresponding to the type of the detection signal to be detected.

Abstract: A driver includes a plurality of output portions; and an output switching control portion. The plurality of output portions is synchronized with a shift pulse signal. The shift pulse signal indicates one specification shift pulse signal among a plurality of specification shift pulse signals. The plurality of specification shift pulse signals indicates a plurality of output numbers which are different from each other based on respective specifications of the plurality of specification shift pulse signals. The one specification shift pulse signal indicates a setting output number as one output number among the plurality of output numbers. The output switching control portion selects a group of output portions corresponding to the setting output number among the plurality of output portions based on the one specification shift pulse signal.

Abstract: Provided is a semiconductor device including a MIM capacitor, and having excellent waterproof property and antioxidant property even when being formed between wiring layers. The semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first wiring layer embedded in the first insulating film, a wiring cap film for covering the first wiring layer, the MIM capacitor formed on the wiring cap film, a hydrogen barrier film for covering the MIM capacitor, a second insulating film formed on the hydrogen barrier film, conductive plugs passing through the second insulating film and the hydrogen barrier film, one of which being connected to an upper electrode of the MIM capacitor and the other of which being connected to a lower electrode of the MIM capacitor, and a second wiring layer connected to the conductive plugs, and the upper and lower electrodes of the MIM capacitor.

Abstract: A receiving circuit includes a frame memory to store received data of one frame, a de-rate matching circuit to generate data before encoding by reading the received data from the frame memory and performing de-rate matching in a reverse manner to rate matching performed on the received data at a transmitting end, and a TTI memory to store the data before encoding.