Abstract: A nonvolatile semiconductor memory device includes a memory array and an X-decode section. The memory array includes a plurality of nonvolatile memory cells arranged in a matrix form and a plurality of word lines. The X-decode section selects a selected word line selected from the plurality of word lines, supplies a negative voltage to the selected word line, and supplies a positive voltage to unselected word lines which are not the selected word line, at the time of an erase operation.

Abstract: A semiconductor memory device includes: a memory array; an internal address supplying unit configured to produce a first internal address in response to an external address; a first fuse unit configured to includes fuses and anti-fuses integrated; an address switching circuit configured to produce a second internal address on the basis of the first internal address; and a decoder circuit configured to select a memory cell of the memory array in response to the second internal address. The internal address supplying unit is configured to be capable of fixing a specific address bit in the first internal address. The second internal address includes: fuse independent address bits produced from address bits which is not the specific address bit in the first internal address, independently of a state of the first fuse unit, and a fuse dependent address bit having a value corresponding to the state of the first fuse unit and a vale of the specific address bit.

Abstract: a data processing apparatus includes: an instruction execution section; an instruction protection information storage section that stores instruction protection information for specifying at least one partial address space in an instruction address space for storing instructions executed by the instruction execution section; a data protection information storage section that stores data protection information for specifying multiple partial address spaces in a data address space for storing operands for use in an operation of the instruction execution section; and a protection violation determination section that determines whether to permit access from the instruction execution section based on setting of the instruction and data protection information storage sections.

Abstract: In an aspect of the present invention, a circuit analyzing method includes: generating an analysis object circuit model by connecting a package model as a lumped parameter circuit model of a package, a noise source model as a lumped parameter circuit model of a noise source circuit, a noise-receiving circuit model as a lumped parameter circuit model of a noise-receiving circuit, and a substrate model as a lumped parameter circuit model of a substrate between the noise source circuit and a noise-receiving circuit; and performing a circuit simulation to the analysis object circuit model to calculate a power supply voltage waveform in the noise-receiving circuit.

Abstract: Disclosed is a temperature sensor circuit including a bipolar differential pair driven by a constant current and having an emitter area ratio of 1:N (N>1) and two MOS transistors having the transistor size ratio of K:1 (K>1) connected as an active load to the bipolar differential pair. A reference voltage is applied to one of the transistors of the bipolar differential pair. The other transistor has a base and a collector connected together. A desired voltage is output between the bases of the two transistors of the bipolar differential pair. A plural number of the temperature sensor circuits may be connected in cascade (FIG. 3).

Abstract: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.

Abstract: Disclosed is a buffer circuit including a source follower circuit comprising a MOS transistor which is driven by a current source. The MOS transistor has a gate to which an input voltage is supplied, a source from which an output voltage is output and a back gate supplied with a back gate voltage for being controlled to provide for a desired value of the source voltage. There is provided a second MOS transistor, to a gate of which a bias voltage is supplied, and a source of which is connected to a non-inverting input terminal of an OP amp.

Abstract: In an optical receiver and amplifier and an optical coupler, a technique for stabilize operations at turning on/off of a power supply by a simple configuration is desired. An optical receiver and amplifier includes: a photodiode generates a photocurrent in response to a light input; an output section outputs output voltage being a low level or a high level in response to a magnitude of the photocurrent by using a power supply voltage supplied from a power supply; and an output control circuit controls an input voltage of the output section such that the output voltage is set to the low level when the power supply is turned on or off during a period where the power supply voltage is lower than a predetermined value. The output voltage can be set to the low level so that an additional circuit for preventing malfunction is not needed.

Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.

Abstract: An operational amplifier according to an embodiment of the invention includes: a control signal input terminal receiving a digital control signal from an external device; first and second transistors as a differential pair of a differential amplifier circuit; a constant current circuit supplying a predetermined current to the differential pair; a first resistor provided between the constant current circuit and the first transistor and involving a first potential difference; and a second resistor provided between the constant current circuit and the second transistor and involving a second potential difference, the operational amplifier changing a resistance value ratio between the first resistor and the second resistor in accordance with the control signal input to the control signal input terminal.

Abstract: A method is provided for driving a display panel including N×3 pixels arranged along each of a plurality of lines extending in a scanning line direction with N being an integer equal to or more than 2, the N×3 pixels constituting first to Nth pixel sets each comprising an R pixel associated with red, a G pixel associated with green, and a B pixel associated with blue. The method is composed of time-divisionally driving the N×3 pixels positioned in each of the plurality of lines. A drive sequence of an nth line out of the plurality of lines is different from that of an (n+1)th line out of the plurality of lines, the (n+1)th line being adjacent to the nth line. The G pixels, each included within associated one of the first to Nth pixels sets, are driven (N+1)th earliest or later for each of the nth and (n+1)th line.

Abstract: A semiconductor device includes an output MOS transistor to control a current flowing into an L-load in accordance with a gate signal input to its gate. A level shifter shifts the level of an input signal based on a power supply voltage at a Vcc terminal to generate the gate signal. A control signal adjuster detects an output voltage between the L-load and the output MOS transistor based on the power supply voltage and adjusts the level of the gate signal.

Abstract: In a laser beam processing apparatus that processes a semiconductor wafer having a multi-layered wiring structure formed thereon, scribe lines defined thereon, and at least one alignment mark formed on any one of the scribe lines, a laser beam generator system generates a laser beam, and a movement system relatively moves the semiconductor wafer with respect to the laser beam such that the semiconductor wafer is irradiated with a laser beam along the scribe lines to partially remove the multi-layered wiring structure from the semiconductor wafer along the scribe lines. An irradiation control system controls the irradiation of the semiconductor wafer with the laser beam along the scribe lines such that the alignment mark is left on the scribe line.

Abstract: A PLL circuit according to an embodiment of the present invention includes: a phase comparator to output an up signal and a down signal based on a phase difference between a reference clock signal and a feedback clock signal; an offset correcting circuit to correct a pulse width of at least one of the up signal and the down signal to output a modified up signal and a modified down signal; a first charge pump circuit to increase or decrease a charge pump output voltage to be output in accordance with the modified up signal and the modified down signal; a loop filter to filter out noise of the charge pump output voltage and generate a filter voltage; and a voltage-controlled oscillation circuit having an oscillation frequency controlled based on a voltage value of the filter voltage and outputting an output clock signal.

Abstract: A data driver includes a positive-polarity reference voltage generation circuit that outputs positive-polarity reference voltages, a positive-polarity decoder that receives the positive-polarity reference voltages from the positive-polarity reference voltage generation circuit, end selects and outputs at least one positive-polarity reference voltage in accordance with first digital data, a positive-polarity amplifier which includes a first differential units that receives the selected reference voltage selected by the positive-polarity decoder, performs amplification, and outputs a voltage to a first amplifier output terminal, ? negative-polarity reference voltage generation circuit that outputs negative-polarity reference voltages, and a negative-polarity decoder that receives the negative-polarity reference voltages from the negative-polarity reference voltage generation circuit, and selects and outputs at least one negative-polarity reference voltage in accordance with second digital data.

Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.

Abstract: In a semiconductor device including a semiconductor substrate, and at least one sensor element made of vanadium oxide formed over the semiconductor substrate, the sensor element is designed so that a density of a current flowing through the sensor element is between 0 and 100 ?A/?m2.

Abstract: In a visual inspection method and apparatus, a picture processing unit converts an original picture, obtained by taking a photograph of a BGA illuminated by a ring illuminator from above, using a camera, and labels a binary picture obtained by this binary conversion. Then, it forms a rectangle circumscribing an outer circumference of a labeling picture obtained by the labeling, and inverts a labeling picture within the formed circumscribing rectangle, and removes a portion of a region formed by the outer circumference and the circumscribing rectangle in a picture obtained by the inversion, and then generates an inspection picture by adding a picture obtained by the removal to the labeling picture, and accordingly judges a pass or rejection of the inspection target sample based on the generated inspection picture. Thus, the inspection can be carried out at high accuracy irrespectively of a low cost.

Abstract: A System-in-Package includes a first chip to be mounted in common for a plurality of product types, a second chip having different specifications for each product type, and a wiring substrate being common to a plurality of product types, on which the first chip and the second chip are to be mounted. A setting signal is supplied from the second chip to the first chip.

Abstract: A driving circuit of a display device including a TFT (Thin Film Transistor) liquid crystal display device or the like is provided which is capable of decreasing a chip in size and reducing costs of testing by reducing the number of bits even in the case of increased number of bits of digital image data to perform multi-gray shade displaying.