Abstract: In an automatic gain control amplifier circuit for an intermittent sequence of digital input signals, a signal detector detects presence and absence of the digital input signal in the sequence to produce a presence signal which takes a presence and an absence level when the digital input signal is present and absent, respectively. The presence signal takes the absence level even upon undesired occurrence of an interruption in one of the digital input signals. A level comparator compares an amplified level of a digital output signal of the amplifier circuit with a reference level, which is preferably equal to an optimum level common to the digital output signals, to produce a comparison result signal which takes a first and a second level when the amplified level is higher and lower than the reference level, respectively.

Abstract: A position control system has a motor for moving a movable member which is driven, at first, by a non-controlled signal. Responsive to a position error signal which represents a difference between a present position and a commanded position, and to a velocity signal which represents a velocity of the movable member, a deceleration signal is generated for positioning the movable member at the commanded position. When it exceeds a predetermined level, the deceleration signal is applied to the motor, instead of the non-controlled signal.

Abstract: A drive circuit which can drive an IGFET in a non-saturated region over a long period time without reduction in level is disclosed. The drive circuit comprises a series circuit of a plurality of directional elements connected between a power supply terminal and an output terminal, a plurality of control terminals receiving repetitional signals and a plurality of capacitors coupled between the control terminals and intermediate junctions of the series circuit.

Abstract: In a data processing system of the type having a processor and a plurality of memory units, which can be accessed simultaneously by the processor, the processor writes simultaneously into both memory units and reads from a particular one of the memory units except when the particular memory unit exhibits an error condition in which case writing and reading are performed in a different memory unit. The switching from the master memory unit to an alternate memory is performed simultaneously with the error indication in the master memory unit during a write operation and is performed at the next clock pulse in a read operation so that a retry can be performed.

Abstract: In a time division multiple access system comprising a central station and a plurality of substations, a subsidiary analog signal is sampled at a sampling circuit of each substation M times during each frame period to produce a succession of sampled pulses. A group of M sampled pulses is located by a substation delay circuit in each up-link burst assigned to each substation. Responsive to an up-link succession including each up-link burst, the central station reproduces the sampled pulse group from each up-link burst into a reproduced group of M reproduced pulses by central station sampling pulses synchronized with the M sampled pulses. The M reproduced pulses are rearranged by a central station delay circuit into sampled pulse reproductions appearing M times in each frame period. The sampled pulse reproductions are desampled into the subsidiary signal. The number of M may be equal to or greater than one.

Abstract: A lead frame for an IC device includes a body element located at its center, the body element including recesses in its outer periphery in which the inner tips of the leads of the lead frame are fitted at predetermined positions. With such an arrangement, the leads are prevented from being deformed during steps of formation of the IC device.

Abstract: An engine ignition control circuit includes a crank angle sensor and two reference position sensors. The engine ignition control circuit also includes an ignition timing control unit generating primary ignition signals and a replacement ignition signal generator device. The control circuit further includes a crank angle monitoring circuit which detects the failure of the crank angle sensor and generates a malfunction signal. The malfunction signal controls a data selector which outputs either the primary ignition signals or the replacement ignition signals to drivers and ignition coils for the engine.

Abstract: There is disclosed a system for the extraction of pole parameter values. The system comprises an autocorrelation value calculating circuit receiving an input voice signal through a time window, for calculating an autocorrelation value V.sub.i (i=0, 1, 2, . . .) of the input voice signal within the time window; a linear prediction coefficient memory circuit for storing linear prediction coefficients (.alpha..sub.1, .alpha..sub.2) corresponding to various pole parameter values; a signal processor for receiving as its input the output value V.sub.i of the autocorrelation value calculating circuit, performing thereon an arithmetic operation according to the following formula using the prediction coefficients (.alpha..sub.1, .alpha..sub.2) supplied by the linear prediction coefficient memory circuit:r.sub.i =(l+.alpha..sub.1.sup.2 +.alpha..sub.2.sup.2)V.sub.i -(.alpha..sub.1 -.alpha..sub.1 .alpha..sub.2)V.sub.i+1 -(.alpha..sub.1 -.alpha..sub.1 .alpha..sub.2)V.sub.i-1 -.alpha..sub.2 V.sub.i-2 -.alpha..sub.2 V.sub.

Abstract: A phase controlled oscillator comprises a first sweeping oscillator producing an output voltage controlled by a control input signal and a first sweeping signal within a limited output voltage amplitude, a second sweeping oscillator which produces a second sweeping signal having an amplitude smaller than that of the first sweeping signal supplied to a phase locked loop, the phase relation of input and output signals of the second sweeping oscillator being selected such that it stops oscillation when the loop is in a locked state, and a control circuit adapted to hold the output voltage of the first sweeping oscillator.

Abstract: The present invention provides an amplifier having cascade-connected first and second transistors, a constant current source for supplying an operating current to the first transistor, and a load resistor connected to the collector of the first transistor at one end and to a substantially constant voltage terminal at the other end. The amplifier arrangement of the invention removes the necessity of a large capacitance capacitor for noise suppression.

Abstract: A gated data burst in a multiplex transmission system is low pass filtered and modulates a carrier wave. The modulated signal has transient skirts on its leading and trailing edges due to the roll-off characteristic of the filter, and these skirts would ordinarily interfere with the signal bursts in adjoining time slots. To avoid this the skirts are clipped off by a further gate signal whose window is slightly wider than that of the first gate, and which is timed such that its edges occur at 0 levels of the burst carrier.

Abstract: A memory circuit which can perform consecutive write operations at a high speed is disclosed. The memory circuit comprises a plurality of bus lines, a plurality of memory cell groups associated with the respective bus lines, a plurality of latch circuits coupled to the respective bus lines, and means for sequentially supplying the bus lines with write data, in which the write data are stored in the latch circuits and transferred to selected memory cells of the respective memory cell groups.

Abstract: A solid-state imaging device has a semiconductor substrate of one conductive type. A plurality of light-charge converter regions, of the opposite conductivity type, are formed in the semiconductor substrate. A charge-voltage converter region, formed in the semiconductor substrate, converts the electric charge produced by the light-charge converter regions into a voltage. At least one charge transfer section is formed in the semiconductor substrate for transferring the electric charge produced by the light-charge converter regions to the charge-voltage converter region. At least one charge transfer gate section is in the semiconductor substrate and has a gate electrode for controlling the timing of a transfer of the electric charges from the light-charge converter regions to the charge transfer section. Pulses are generated with a predetermined pulse potential and applied to the gate electrode in the charge transfer gate section. The predetermined pulse potential has the relationshipV.sub.B +2.phi..sub.

Abstract: In an electronic circuit comprising a modulator (35) and used in each substation of a TDMA system and responsive to a baseband data signal sequence for producing a burst in accordance with a first burst control pulse, spurious components resulting in the burst from the first burst control pulse are eliminated either by allowing the data sequence to pass through a low-pass filter (36) after switching (45) the sequence by the first burst control pulse or by filtering the first burst control pulse by a low-pass filter before switching a local oscillation signal by the first control pulse. An additional switching circuit may switch either a modulated signal supplied from the modulator or the local oscillation signal in response to a second burst control pulse that disappears after extinction of the first burst control pulse.

Abstract: A buffer memory system comprises a buffer memory and a fetch directory. Both are accessible by a concatenation of at least the least significant bit of logical or physical page field of a logical or a physical address signal and a selected number of bits lower than that least significant bit. Physical page fields stored in the fetch directory are used to control an access to a data block stored in the buffer memory even at a plurality of addresses accessible by logical and physical address signals for one and the same instruction for accessing the memory. The system may or may not comprise an inverse translation table for translating a physical address signal for accessing a main memory into the concatenation to be used in accessing the buffer memory and the control table.

Abstract: An optical multiplexer/demultiplexer is used in a wavelength division multiplexing. An optical energy transmission body has N side faces, where N is equal to or larger than three. A first predetermined one of the N side faces directs a single beam of radiant energy, at a predetermined angle, into or out of the body for carrying out the demultiplexing or multiplexing operation. The single beam contains M preselected wavelengths, where M is equal to or smaller than N-1. A plurality of beam passing means are associated in a one-to-one correspondence with (M-1) of the N side faces. The beams which pass through the M-1 side faces contain a corresponding one of M wavelengths and reflect a beam containing at least one of the M wavelengths, other than the corresponding wavelength. Another of the N side faces passes a beam which is finally reflected by the plurality of beam passing means.

Abstract: There is provided a code converting circuit for converting digital signals of fixed length codes into variable length codes and delivering a train of variable length codes produced by the conversion parallelly every predetermined K bits.

Abstract: An improved protective device for the gate insulation of an integrated-gate field effect transistor (IGFET) is disclosed that does not breakdown under spike-like input voltages. The protective device is formed on the same semiconductor chip as an operative IGFET and includes a resistor connected between the input terminal and the operative IGFET's gate, a protective IGFET whose drain and gate are both connected to the operative IGFET's gate, and another resistor connected between the protective IGFET's source and a constant voltage source.

Abstract: A high-density integrated circuit is disclosed, which comprises at least three stacked wiring layers, the lowest layer being formed of polycrystalline and including silicon gates of a plurality of insulated-gate field-effect transistors, one of the upper layers being formed of polycrystalline silicon and used for feeding a power supply to the transistors, and the other of the upper layers being formed of high-conductivity metal. Where the upper polycrystalline silicon wiring layer is under the metal wiring layer, it is preferably of a mesh-like pattern.

Abstract: In a pulse detector of a receiver for use in a digital radio communication system comprising a low pass filter supplied with an input signal, a first resistor and a capacitor which are connected in series between an output terminal of the low pass filter and ground to constitute a longer time constant integrating circuit, a second resistor connected in parallel with the first resistor through a switch controlled by a control input, the first and second resistors and the capacitor constituting a shorter time constant integrating circuit, and a comparator with one input connected to the output of the low pass filter and the other input to a juncture between the first and second resistors and the capacitor, the potential of the juncture being utilized as a reference potential of the comparator, there is provided a switch connected between the juncture and the ground in series with the capacitor.