Abstract: In a run length decoding apparatus of the type comprising a decoding circuit decoding a series of run length encoded data to sequentially output binary data indicative of respective run lengths, and decoding means for decoding a white or black signal having a number of bits represented by an output value of the decoding circuit so as to sequentially accumulate decoded signals in a picture memory device, there are provided a lower order counter to be set with a surplus less than n (an integer larger than 2) of the output value of the decoding circuit, an upper order counter to be set with an upper order value, count of the upper order counter being decremented according to a clock pulse, a selector which, in response to a carry signal outputted by the upper order counter, selects and outputs either one of a fixed value n and an output signal of the lower order counter at each clock pulse, a flip-flop circuit whose state is reversed at each one run length, and an array conversion circuit inputted with decoded d

Abstract: In a pattern matching method, the input pattern of a character is compared with each of a plurality of standard patterns to detect similarities and differences by counting the number of pattern elements which are or are not matched with each other. To do this, a high-speed comparator stores a plurality of comparing data in a memory, which is driven by a clock pulse train. The memory produces a plurality of sequence signals during each time interval when the clock pulses of a number responding to a plurality of comparing data are applied thereto. The first or last produced sequence signal is detected from among the plurality of sequence signals and is used to extract the maximum or minimum data.

Abstract: In a switched capacitor filter of a first-order responsive to a filter input signal for producing a filter output signal by carrying out sampling operation at a predetermined sampling rate by the use of switching circuit, a capacitor, and an integrating circuit, a voltage divider produces a voltage divided signal in response to the filter input signal to reduce a total capacitance determined by capacitances of the capacitor and the integrating circuit. The voltage divided signal is sampled by the switching circuit to be sent to the integrating circuit at the sampling rate through the capacitor. The integrating circuit produces the filter output signal as a result of integration. In addition, an additional switched capacitor filter of a first-order is connected in cascade to the filter to form a switched capacitor filter of a second-order.

Abstract: A negative feedback amplifier has an amplifying section including a first GaAs FET with its source, gate and drain electrodes. A second GaAs FET has its drain electrode connected to the source electrode of the first GaAs FET. An input terminal is connected to the gate electrode of either the first or the second GaAs FET. A feedback circuit feeds back a part of the output given from the drain electrode of the other GaAs FET's to the gate electrode of the same GaAs FET.

Abstract: A limiter amplifier with a power supply has a plurality of cascade-connected differential amplifiers for limiting the amplitude of an input signal. Each of the amplifiers has a first constant current circuit. A biassing circuit, having a second constant current circuit, is connected to the input of the differential amplifier for supplying its biassing needs. A third constant current circuit activates the first and second constant current circuits. A voltage regulator is connected to the power supply for providing a constant voltage to each of the three constant current circuits. The voltage regulator and the first to third constant current circuits have the same temperature characteristics.

Abstract: A tabulation system for delivery to a medium of data information suitably arranged for tabulation of character series and ruled lines, and a control for controlling the data information arrangement applied to the medium. The control operates to allow the medium to sequentially deliver out control information for defining desired vertical ruled lines (columns), information regarding a horizontal ruled line (row) defining the upper side of a field between adjacent vertical ruled lines, information regarding character series to be written in the field and control commands for the writing, and information regarding a horizontal ruled line defining the lower side of the field.

Abstract: An engine ignition interpolation apparatus including three reference position sensors, a single crank angle sensor and a counter resettable by outputs from the reference position sensors and used for counting output pulses from said crank angle sensor. Also included are a decoder for generating an output when the counter produces a count output which exceeds a preset value, flip-flops connected respectively to the reference position sensors in a ring arrangement and triggerable by the outputs from the reference position sensors for synchronous operation therewith, and a logic circuit for seeking conformity between the output from the decoder and set outputs from the flip-flops to produce a quasi or replacement pulse for one of the reference position sensors which fails to produce an output, thereby interpolating a reference position pulse.

Abstract: An amplifier switchable between a dual-channel amplifier and a BTL amplifier includes first and second amplifying circuits having a non-inverting input, an inverting input and an output, a first input terminal receiving a first input signal and applying it to the non-inverting input of the first amplifying circuit, a second input terminal receiving a second input signal, a first switch selectively applying a signal to the non-inverting input of the first or second amplifying circuit, a second switch controlling the application of an output from the first amplifying circuit to the inverting input of the second amplifying circuit, a controlling circuit controlling the first and second switches, first through third loads and a third switch controlling the application of an output from the first and second amplifying circuits to the first and second loads, respectively, or to the respective ends of the third load.

Abstract: Apparatus for generation of binary pseudo-random numbers of n bits by use of the maximum-length shift register sequence based on a primitive polynomial, f(x)=x.sup.p +x.sup.q +1, where p and q are positive integers satisfying the relation p>q.gtoreq.1. The apparatus comprises p-bit storage means; (p-q) bit shift means for shifting the contents of said p-bit storage means; exclusive OR means for exclusive-ORing m (m.gtoreq.n) bits resulting from the shifting and consecutive m bits stored in said storage means bit by bit; means for restoring exclusive-ORed results to uppermost bits of said storage means and uppermost (p-m) bits of said storage means to lowermost (p-m) bits thereof; and means for extracting uppermost n bits from said storage means.

Abstract: An improved counter wherein consecutively cascaded flip-flops of the prior art are divided into two groups. A first detector produces a first signal in response to a predetermined set of flip-flop states of the first group. A second detector produces a second signal in response to a predetermined set of flip-flop states of the second group. A third detector produces a count output in response to simultaneous existence of the first and second signals. The output from the first group is arranged in phase so that the second signal may be produced before the count output is produced, by applying an inverted output of the first group to the input of the second group.

Abstract: A display control system has a memory for storing display information and a memory access circuit for reading display information out of this memory. This memory access circuit includes a first circuit in which a memory address is set, a second circuit for sequentially varying the memory address by a predetermined value, and a third circuit for adding to the memory address a preset value, which is different from the predetermined value. A control circuit gives a designation of the addresses to the memory, as a result of the cooperation of the second circuit and the third circuit. The control circuit can be achieved so that display information is read while a memory address may be varied by at least two different means (the second and third circuits above). Thus, it becomes possible to selectively designate a part of a memory region and to display the information of the selected memory region.

Abstract: In a portable radio receiver of the type wherein a metal member forming a loop antenna surrounds the circuit components making up the receiver circuitry, the receiver is provided with high impedance elements in series with at least the power supply and grounding lines at some point between the power supply and the RF-IF converter. The antenna circuitry may also include a high impedance element in series with the signal path at some point downstream of the RF-IF converter.

Abstract: A semiconductor circuit having an improved current switching function is disclosed. The circuit comprises at least one current switch unit including a current source, a current output node, a field effect transistor connected between the current output node and the current source, an inverting amplifier having an output supplied to a gate of the field effect transistor and an input connected to the junction point of the current source and the field effect transistor and means for controlling operation of the amplifier.

Abstract: A surface acoustic wave bandpass filter has a piezoelectric substrate for propagating a surface acoustic wave. An input transducer is formed on the substrate, with a pair of interdigital electrodes, for exciting a surface acoustic wave in response to an electrical signal. An output transducer is also formed on the substrate, with essentially the same structure for developing a filtered electrical signal from the surface acoustic wave propagated in the substrate. The input and output transducers are arranged so that the distance between them (L) satisfies the relationship: .lambda./2 n<L<.lambda./2 (n+1) (n is a positive integer), and .lambda./2 represents the distance between the centers of adjacent electrode fingers.

Abstract: A rotational angle detection device having two magnetoresistive sensing elements positioned at a 45.degree. angle with respect to each other senses the rotary position of a permanent magnet. Sine and cosine waves are applied to first and second bridge circuits respectively incorporating the two sensing elements. The resulting bridge circuit outputs are differentially combined to provide an output whose phase relative to either of the input sine or cosine waves is dependent upon the rotational position of the permanent magnet. The phase difference is detected and the rotational position is calculated therefrom.

Abstract: A subscriber line circuit comprises a controllable DC to DC converter (41) for producing a converter output signal which becomes a loop signal comprising a DC signal and/or a communication signal of a communication frequency band. First and second voltage signals are dependent (51, 69) on the current and the voltage of the loop signal, respectively. One of the voltage signals is amplified (71) with different transfer functions at DC and in the communication frequency band. The converter is controlled (85-86) by an error between a first sum (81) of the amplified signal and the other voltage signal and a second sum (82) of a reference voltage (E.sub.O) and a signal supplied from an output (27) of an exchange. A subtractor (92) supplies a difference between the exchange output signal and the second voltage signal to an input (25) of the exchange. Preferably, terminals (16, 17) for connection to a subscriber substation are isolated at DC from terminals (18, 19) for connection to the exchange input and output.

Abstract: A single data signal is transmitted by two transmitters to two radio zones having an overlapping zone therebetween. The data signal is frequency or phase modulated and is mixed in the transmitters with RF carrier waves of equal frequency. The data signal to one of the transmitters is delayed between 5.degree. and 50.degree. with respect to the original data signal to provide a phase difference between the transmitted signals.

Abstract: A bandpass filter has a line extending from an input terminal to an output terminal. Three stubs are connected to the line at three different locations on the line at a spacing which is 1/8 of the wavelength, at the center frequency of the passband. Each of the three stubs is short-circuited at a first end and open at a second end and has a total length which is 1/4 the wavelength of said center frequency. The outermost of the three stubs is connected to the transmission line, at a position which is 1/6 the wavelength, from the first end. The intermediate of the three stubs is connected to the line at a position which is either 1/8 or 1/4 the wavelength of the center frequency.

Abstract: In a signal processing device, such as a television receiver, a multiplex signal processing circuit with a switching device for selecting either a first image signal and a second image signal. A clamping circuit is provided for clamping the pedestal potential of the second signal at a reference voltage, a comparator compares the pedestal potential of the first signal with the reference voltage, and the pedestal potential of the first signal is equalized to the reference signal in accordance with the comparator output.

Abstract: A frequency divider is provided by coupling the gate current paths of a pair of Josephson junction gate circuits in parallel with the control current path of a third Josephson junction gate circuit being connected in series with the gate current path of one of the first pair of Josephson junctions. The gate current path of the third Josephson junction is connected in series with the control current path of the other of the first pair of Josephson junctions, and an input signal to be frequency divided is connected in common to the connection point of the control current path of the first Josephson junction and gate current path of the third Josephson junction. Current flowing through the control current path of the first Josephson junction will be at one-half the frequency of the input current. A plurality of frequency dividers may be cascaded to perform 1/2.sup.N frequency division.