Abstract: A pattern matching device generally comprises a first circuit (36) for calculating an elementary similarity measure between two feature vectors, one and the other selected from two feature vector sequences representative of two patterns, respectively, and a second circuit (37) for iteratively calculating a recurrence formula which defines a recurrence value by a sum of such an elementary similarity measure and an extremum of a prescribed number of previously calculated recurrence values. The recurrence formula eventually gives an overall similarity measure between the two patterns. The elementary similarity measure is now calculated by calculating a primitive similarity measure by a conventional circuit (15) and subtracting a predetermined value therefrom by a compensation circuit (31). Preferably, the second circuit (37) comprises circuitry (41, 42) for preventing the sum from overflowing outwardly of a preselected range.

Abstract: A 2.sup.N -phase phase modulator is formed from a plurality of series-connected 2-phase phase modulators. Each of the 2-phase phase modulators includes an Exclusive OR gate receiving at one input terminal one of a plurality of digital data sets. The first phase modulator receives a carrier signal at its other input terminal, and all subsequent phase modulators receive an output from a previous phase modulator through a 1/2 frequency divider.

Abstract: A cross-polarization crosstalk canceller is equipped to receive two polarized waves which are orthogonally crossing each other. The cross-polarization interference is eliminated by multiplying the signal received on one side by a compensating coefficient and adding the resulting product to the signal received on the other side. A discrimination error represents the difference between the reception signal after compensation and the identified value thereof. An adder and a subtractor supplies the sum and the difference between the real part and the imaginary part of the discrimination error. A discriminator detects equality between the absolute values of the real part and the imaginary part of the signal received on the interfering polarized wave side and supplies a control signal depending on the quadrant to which the signal belongs. A switch combines and varies a combination of the signs of the outputs of the adder and subtractor in response to the control signal supplied by the discriminator.

Abstract: An electronic detection circuit recognizes a test signal and causes the battery saving feature in a paging receiver to be suspended for a testing period. During testing and receiving periods, battery power is continuously supplied to a receiving circuit. At other times, power is intermittently supplied to the receiving circuit in a prescribed cycle.

Abstract: A radio pager receives a signal having a selective calling signal portion and message signal portion and examines the selective calling portion of the signal for its own ID code. Upon detecting a match, an alert signal is provided and the message signal portion is stored in a memory if it does not match any of the message signals already stored. A counter also keeps track of the number of stored messages. The messages can be sequentially displayed when desired.

Abstract: A radio paging receiver is provided in which messages are continuously written into a first memory for subsequent display. A second memory is used to selectively prevent the erasure of messages written into the first memory when the first memory capacity has been exceeded.

Abstract: A vertical PNP transistor having a large withstand voltage is disclosed. On a P-type substrate, a N-type epitaxial layer is provided. A P-type isolation region is formed in the epitaxial layer as a closed-loop to isolate a portion of the epitaxial layer from the other portions thereof. A first N-type buried layer is formed in the isolated epitaxial layer at the interface of the epitaxial layer and the semiconductor layer so as to separate the two. A second P-type buried layer is provided on top of the first buried layer. A P-type collector region is formed as a second closed-loop in the epitaxial layer enclosed within the first closed-loop. A high N-type concentration region that permits great withstand voltage is formed as a closed-loop separating the first closed-loop and the second closed-loop regions. A P-type emitter region is formed in the epitaxial layer region enclosed within the second closed-loop. Without the emitter region, the device can be used as a diode.

Abstract: An antenna having a frequency separator of the type comprising plural lattice structures of a periodic conductive pattern. Each lattice structure exhibits an inherent resonance frequency and an inductance-capacitance effect at frequencies below the inherent resonance frequency. The periodic conductive patterns are selected so that each of the lattice structures exhibits substantially the same inherent resonance frequency, and when placed at selected intervals, the plurality of lattice structures exhibit interactive resonance at frequencies below the inherent resonance frequencies. Each lattice also exhibits substantially equal inductance and capacitance with respect to obliquely incident electromagnetic waves in the TE and TM modes.

Abstract: An optical coupler formed on a substrate including a plurality of input and output guide channels and an immediate mixing guide channel connecting the input and output guide channels wherein the optical coupler comprises substantially V-shaped grooves on the substrate disposed in the ends of the input and output guide channels for receiving optical fibers.

Abstract: In an encoder responsive to a video signal variable between high and low levels, a logic converter logically converts a succession of result signals, derived from the video signal by the use of a predetermined number of halftone threshold levels, into a sequence of converted signals having that run length of logic "0" or "1" level which is longer than that in the result signal succession. The converter may comprise a combination of adders and memory elements to process the consecutive result signals. The converted signal sequence is encoded by an encoding circuit into a data-compression digitized signal. In a decoder for decoding the digitized signal into a reproduction of the result signal succession, a logic inverter comprises a combination of adders and memory elements, similar to that of the converter. The inverter processes, into the reproduction, signals derived from data-expansion decoding of the digitized signal. Preferably, a dither matrix is used to provide the threshold levels.

Abstract: A binary pattern signal producing apparatus for optical character recognition comprises a pre-scanning section for determining an area containing the information to be scanned, a scanning apparatus for producing a signal in accordance with the luminance of the scanning area, an automatic gain control circuit for controlling the level of the information signal in accordance with the level of a portion of the same information signal representing less than the entire scanned area, and a comparison circuit responsive to the output of the automatic gain control circuit for generating the binary pattern signal. In addition to or in place of a gate circuit which is used to provide only a portion of the information signal to the gain control terminal of the automatic gain control device, the apparatus may include noise eliminating circuitry for removing pulsive noise from the gain control signal.

Abstract: For use in a packed nine-bit-byte data processing system, a shift circuit comprises a shifter for subjecting a datum given by a bit sequence of nine-bit bytes to a shift of a preselected whole number N of digits or, more particularly, a shift of [9N/2] and [9(N-1)/2+5] bits when the whole number is an even and an odd integer, respectively. Before written in a register, the shifted bit sequence is edited by an editor into an edited bit sequence wherein each prescribed binary bit in each nine-bit byte is produced as it stands when the whole number is even and is placed, when the whole number is odd, at a next more significant bit than a four-bit byte which is next more significant in the shifted sequence than that binary bit.

Abstract: In a transmission system of a class IV partial response code succession produced in accordance with a predetermined encoding rule, a transmitter intentionally violates the encoding rule to carry a subsidiary signal, so that an intentional violation appears in a receiver as two consecutive violation signals located in every other time slot, differing from an unintentional violation occurring during transmission. In the transmitter, an intermediate succession from a precoder is monitored by a detection circuit to detect an appearance of each predetermined pattern and to give the intentional violation to the code succession. In the receiver, a violation detector detects both of the intentional and the unintentional violations in accordance with a detecting rule to produce a violation signal sequence. The two consecutive violation signals are distinguished from the violation signal sequence by another detector.

Abstract: In a digital transmitting system wherein signal information is transmitted from a transmission buffer memory device to a receiving buffer memory device through a transmission line extending therebetween, there are provided a counter for producing count information proportional to a sum of information transmission delay times in the transmission and receiving buffer memory devices, and a read control circuit which controls the read-out time of the information from the receiving buffer memory device such that a count of the counter coincides with a predetermined reference value, thereby rendering a sum of the information transmission delay times coincident with a predetermined time.

Abstract: This invention provides a flip-flop drawing low current and occupying a small area in a semiconductor integrated circuit. The flip-flop has a first and a second transistor having their emitters grounded via a first and a second diode, respectively. The collector of the first transistor is coupled with the base of the second transistor via a third diode. Likewise, the collector of the second transistor is coupled with the base of the first transistor via a fourth diode. The output is derived from the collector of a third transistor having its base-emitter path connected in parallel with the first or second diode to form a current mirror circuit.

Abstract: In a plastic or resin encapsulated semiconductor device, the bonding pad electrodes cannot be covered by a waterproof film. Moisture easily penetrates the plastic or resin coating and/or the boundary between the coating and the bonding wire reaching the phosphorus silicate glass under the bonding pad electrode. This penetrated moisture produces phosphoric acid which in turn corrodes the bonding pad electrodes. The present invention prevents the corrosion of the bonding pad electrodes by eliminating the phosphorus silicate glass under the bonding pad electrode or by separating the bonding pad electrode from the phosphorus silicate glass.

Abstract: A thermally addressable liquid crystal display device is disclosed herein. The device comprises twin transparent plates with a liquid crystal element disposed between them. A transparent electrode film is provided onto the inside surface of the first transparent plate (the inside surface being that surface which is in contact with the liquid crystal element). Both a light-reflecting film and a light-absorbing single layer are provided onto the inside surface of the second transparent plate. This light-absorbing layer is formed of an inorganic semiconductor compound selected from the group of II-V group semiconductor compounds containing magnesium or calcium, II-V group semiconductor compounds containing zinc or cadmium, or II-VI group and V-VI group semiconductor compounds containing tellurium. Preferably, the light-absorbing layer has a thickness which satisfies the relationshipt=.lambda./4n.+-..lambda./20nsuch that the resulting image display is high in image resolution.

Abstract: In an integrated optical semiconductor device wherein a stripe geometry laser diode is separated from a photodetector by an etched groove, the stripe region has a smaller width, such as 2 to 3 microns, than a carrier generating region of the photodetector. The stripe region is preferably rendered thicker than the carrier generating region, in which case the carrier generating region is more preferably made of a seimconductor material having a narrower band gap than the material of the stripe region. The stripe region may be defined by a buried mesa structure. Alternatively, the stripe region may be bounded transversely of a pair of heterojunctions therefor by a pair of channel-shaped regions of a semiconductor material having a wider bank gap than the material of the stripe region. In this event, the carrier generating region is divided into three parts by extensions of the channel-shaped regions.

Abstract: The inventive system includes a central station and a plurality of satellite stations which communicate on a time division multiplex basis. The central station generates frame synchronizing and clock signals, along with digital communication signals, which are suitably modulated into channel time slots. During its individually assigned channel time slot, each satellite station extracts the frame and clock signals and demodulates the communication signals which were directed to it. The extracted frame and clock signals are used in the satellite station to retime the communication signals which are sent in bursts of modulated carrier waves from the satellite stations to the central station. The central station demodulates the bursts of carrier waves to transmit the intelligence therein to its destination. The advantage is that many stations can share the same frequency and thereby make more efficient use of the transmission capacity.

Abstract: An ignition coil control circuit compares the coil input current with a reference level, and the duty ratio of the output current is altered accordingly. The reference level is raised during cold weather operations, raising the duty ratio. Once the operating temperature of the engine rises above a predetermined level, a detector circuit activates a control signal generator which lowers the reference level received by the comparator to lower the duty ratio accordingly.