Abstract: In a power supply system for use in a radio communication system comprising a base station for transmitting and receiving radio signals, one or more repeater stations for repeating the radio signals, and a terminal station communicating with the base station through the repeating stations, the base station comprises means for transmitting synchronizing signal pulses at a predetermined period for effecting a battery saving type power supply. Each of the repeater station and terminal station comprises means, responsive to successive reception of a predetermined number of the synchronizing signal pulses, for effecting intermittent battery saving at a period substantially equal to the period of the synchronizing signal pulses during occurrence of the synchronizing signal pulses.

Abstract: An antenna duplexer is made compact by a use of a SAW filter, and yet it eliminates the possibility that the SAW filter might be burned, and it avoids additional circuits, e.g., an impedance compensation circuit. The antenna duplexer comprises a local oscillation filter. A reception filter is coupled to the local oscillation filter. The coupled side is partly constituted by a SAW filter. A transmission filter is coupled to the reception filter and an antenna is coupled between the reception filter and the transmission filter.

Abstract: A television system (for example) may transmit a stream of signals in the form of successive binary words. The signal transmission channel may be used much more efficiently if these binary words are compressed by a reduction of the signal bits before transmission or expanded after transmission in order to reconstitute the original signal. Regardless of why the signals are compressed, the invention improves the transmission quality by sending a combination of fixed length and variable length binary words. This is done by providing a fixed length signal converter in parallel with a variable length signal converter. A decision-making circuit separates the successive binary words responsive to logical decision-making rules relating to an average length word. A selector switch selects between the outputs of the two converters responsive to the logical decisions.

Abstract: A NAND logic gate circuit having a first input circuit receiving a first input signal, an inverter circuit for inverting the output of the first input circuit, a second input circuit for receiving a second input signal, an AND gate circuit for producing a logical AND output signal in response to the outputs of the inverter circuit and the second input circuit, and a PNP transistor responsive to the second input signal having a low value for controlling the value of the output signal of the first input circuit independent of the value of the first input signal. The NAND gate circuit has a faster response time to changes in the value of the first input signal than comparable prior art circuits and reduces the current flow to the second input terminal when the first input signal is high and the second input signal is low.

Abstract: A liquid crystal display device comprising a liquid crystal composition filled between one pair of electrode substrates at least one of which is transparent, said liquid crystal composition containing one or more blue dye(s) represented by the following general formula: ##STR1## wherein one of X and Y is amino group and the other is hydroxyl group; and R is alkyl group, alkoxy group, alkylthio group, aryl group, aralkyl group, aryloxy group, arylthio group, aralkyloxy group, aralkylthio group, halogen atom, piperidino group, piperazino group, morpholino group, pyrrolidino group or a group ##STR2## in which R.sub.1 and R.sub.2 are hydrogen atom, alkyl group, aryl group or aralkyl group; provided that the alkyl chain and the aryl ring in substituents R, R.sub.1 and R.sub.2 may optionally be substituted.

Abstract: A pulse generator utilizes a Josephson junction gate circuit having first and second control current paths for conducting control currents in opposite directions. An input signal applied to one of the control current paths will transform the Josephson junction device to the voltage state resulting in the leading edge of a pulse output from a branch circuit connected in parallel with the gate current path of the Josephson junction device, and the same input pulse passed through a delay circuit will be applied in the opposite direction to the other control current path to thereby switch the Josephson junction device back to the zero voltage state and cause the trailing edge of the pulse output. The delay device can be a .pi. circuit, a single additional Josephson junction device having its control current path connected either in series or in parallel with the one control current path of the first Josephson junction device, or a plurality of cascaded Josephson junction devices.

Abstract: A PAL digital video signal processing arrangement includes converter circuitry for sampling a PAL system video signal in response to sampling pulses having sampling points associated with .+-.U and .+-.V modulation axes on a color vector plane to convert an analog composite video signal containing a luminance signal and a color subcarrier into a digital video signal, and a modulation axis inverting configuration for inverting the polarity of the digitized color subcarrier at the sampling points associated with the .+-.V axis.

Abstract: An amplifier or oscillator transistor circuit with low power consumption has a first transistor for amplification or oscillation and a biassing circuit for supplying a D.C. biassing voltage to the base of the first transistor. The biassing circuit comprises a voltage dividing resistor having an output terminal for providing a divided D.C. voltage. A second transistor has an emitter follower circuit with a base which is connected to the output terminal. Its emitter is coupled to the base of the first transistor to provide the D.C. biassing voltage. Furthermore, the first transistor means has an inverse conductive junction accompanied to the junction of the second transistor.

Abstract: In a control signal generator, a first frequency dividing circuit controllably frequency divides a television subcarrier signal to deliver a first frequency divided signal to a phase lock loop, which drives a logic circuit to produce a control signal for use in a television signal codec. Together with the first frequency divided signal, a second frequency divided signal produced by frequency dividing horizontal or vertical synchronizing signals, is supplied to a phase control circuit for phase controlling the first frequency divided signal so as to keep a phase difference which the first frequency divided signal has relative to the second one, within a prescribed tolerance. When the phase difference is smaller and not smaller than the tolerance, a switch may selectively supply the phase lock loop with the first and the second frequency divided signals, respectively, with the first frequency divided signal phase controlled to the tolerance if the phase difference is not within the tolerance.

Abstract: A digital to analog converter having an improved conversion linearity is disclosed.The digital to analog converter comprises means for receiving an input digital signal (1), means for dividing the first digital signal to a plurality of digital signals (2, 3), a plurality of conversion means (8, 9) for converting the divided digital signals to analog signals, respectively, and means (10) for summing the analog signals to produce a summed analog signal corresponding to the input digital signal.

Abstract: An input/output unit modifiable engine ignition control apparatus for controlling ignition timing for engine cylinders at optimum values based on reference position pulses, crank angle pulses generated and a vacuum signal produced by reference position sensors, a crank angle sensor and a vacuum sensor mounted in an engine. The engine ignition control apparatus is divided into an input-output unit and a control unit. The control unit having a control capacity for an engine having a maximum number of the sensors and engine cylinders, so that the control unit can be shared by a variety of engines for their ignition control simply by changing the input-output unit.

Abstract: An optical fiber interconnection mechanism has a casing frame and a plurality of housing units vertically stacked therein. Each of the housing units has a top plate, a bottom plate, two opposed side plates and a back plate with a plurality of fiber guide ring members. A protecting cover plate is removably mounted on the front of the corresponding housing. At least one optical terminal plate is arranged horizontally between the two opposed side plates and has a plurality of optical sockets for making connections with optical fibers. A plurality of excess fiber length storage plates are located at the rear of the terminal plate. A plurality of sets of radially arranged winding saddles are positioned on the storage plates for receiving the excess lengths of the fibers connected to the optical sockets.

Abstract: A memory control apparatus includes a pair of equal capacity cache memories, one for storing a portion of the instructions located in the main memory and one for storing a portion of the operand data located in the main memory. Each cache memory has an address array and a data array which operate in response to an instruction address from an instruction fetch unit or an operand data address from an operand fetch unit or an operand execution unit. If the instruction or data called for is not in the cache memories, it is taken from the main memory and a copy is placed in an available storage location in the cache memory.

Abstract: For use in deciding whether a single or a t-tuple error (t being greater than unity) is present in each bit sequence given as a primitive BCH code in accordance with a generator polynomial comprising a primitive and a non-primitive polynomial, an error checking circuit comprises first and second dividers (16, 17) for dividing each bit sequence by the primitive and the non-primitive polynomials to provide first and second signals, respectively. If the bit sequence includes only a single error, the first signal represents one of non-zero residues which result by the division when such single errors are present at the respective bit locations of the sequence. A memory (18) is preliminarily loaded with reference numbers corresponding to the respective non-zero residues and produces one of the reference numbers in response to the first signal only in the presence of a single error. A comparator (19) compares the produced reference number with a residue represented by the second signal to carry out the decision.

Abstract: In an interference elimination device for use in a digital microwave communication system in which an interference component results from at least one different microwave communication system sharing a frequency band in common, a controller (21) controls a device input signal so that a controlled signal thereby produced may include a controlled component which is equal in amplitude to the interference component and be antiphase relative thereto. The controlled signal is subtracted from the device input signal to provide a difference signal which is free from the interference component. Together with the device input signal, the difference signal is supplied to a control signal producing circuit (41) for producing an amplitude and a phase control signal for the controller. Instead of the device input signal, an interference signal derived by causing the device input signal to pass through a narrow-band filter (11 or 12) may be delivered to the controller and the control signal producing circuit.

Abstract: A control unit modifiable engine ignition control apparatus for controlling ignition timing optimally for each cylinder by processing reference position pulses, crank angle pulses and a vacuum signal generated by a reference position sensor, a crank angle sensor and a vacuum sensor which are mounted on the engine. The engine ignition control apparatus is divided into an input-output section including an input-output unit and a controller comprising a single or a combination of control units each having a minimum capacity to control a single ignition coil.

Abstract: A frequency modulation transmitter has a frequency synthesizer comprised of a voltage controlled oscillator for operating a transmitter section of the modulation transmitter. The output center frequency of the voltage controlled oscillator is determined by channel designation information. The level of a modulation input signal applied to the voltage controlled oscillator for modulating the center frequency is changed in accordance with the channel designation information.

Abstract: A memory circuit capable of detecting that refresh operation is surely ended is disclosed. The memory circuit comprises a memory cell matrix, a dummy array sharing rows with the memory cell matrix and similar column structure to the memory cell matrix, and means coupled to a pair of digit lines of the dummy array for detecting that a potential at either of the pair of digit lines in the dummy array reaches an amplified low level.

Abstract: In a loop transmission system in which packet communications are made among a plurality of transmission/reception terminals which are connected in a loop, a higher degree of priority is given to a real time signal packet, while a lower degree of priority is given to a data packet. A communication path in each terminal is controlled according to the degree of priority such that a packet having a higher degree of priority will not be delayed when it passes through the terminal. Further, a transmission request command signal having an intermediate degree of priority is sent for effecting a real time signal transmission as well as full dual communication. In a modified embodiment, a traffic quantity detector is provided for sending out a real time information message. In another modification, an activity control circuit is added for controlling sending out of the voice packet according to a detected traffic quantity.

Abstract: A mail tracing apparatus contains only input and output mail article detectors at the beginning and end of a mail transport path, respectively. By comparing the "on" and "off" times of the detectors at either end of the path, it can be determined, for example, if an initially doubled item has been separated into distinct mail articles, or if a mail article has dropped out of the path during transport.In either event, an error code is generated in the event of a non sequitur, and the tracing of subsequent mail articles may proceed without error.