Abstract: An information processing system has a bus for providing information transmission, which is received at an external terminal. An input/output circuit is coupled between the bus and the external terminal for effecting the information transmission therebetween. A first control signal controls the timing of the input/output circuit so that the information may be transmitted from the bus to the external terminal. A second control signal controls the timing of the input/output means so that the information may be transmitted to the bus. A third control signal has a timing which is different from both the first and the second control signals so that the information may be transmitted through the input/output circuit. Timing control means selectively applies the first or second control signal and then the input/output circuit operates in accordance with the third control signal.

Abstract: A Faraday rotator has a non-magnetic garnet substrate with a ferrimagnetic garnet film epitaxially grown on the substrate. A magnet induces a magnetic field in the film for rotating the plane of polarization of a light-beam which strikes an end surface of the film at a predetermined angle. The substrate and film are composed of a material wherein the difference (.DELTA. a=a.sub.s -a.sub.f) between the lattice constant a.sub.s of the substrate and the lattice constant a.sub.f of the film satisfies .vertline..DELTA.a.vertline..ltoreq. 0.001A (angstrom).

Abstract: A digital signal communication system has a transmitter for differentially converting first digital signals of n trains (n is an integer of 3 or larger) into a second digital signal of n trains comprising a plurality of words. Responsive to the second digital signals, a modulated signal is provided with 2.sup.n (=N) modulation levels, which are transmitted. A receiver responds to the modulated signals, and demodulates them to provide signals of n trains corresponding to the second digital signals. This demodulated signal is differentially converted to provide n trains of signals corresponding to the first digital signals. The Hamming distance between two words of said second digital signals corresponding to the adjacent two modulation levels is either 1 or 2 and the numbers of the Hamming distances of 1 and 2 equal N/2, respectively.

Abstract: A two-dimensional, imaging device has a semiconductor substrate of one conductivity type, an orthogonal array of photosensitive regions of opposite conductivity type, charge transfer gates and charge transfer channels separating columns of the orthogonal array. A gate pulse generator applies a gate pulse to the charge transfer gates. A clock pulse generator applies a two phase clock to the charge transfer channels. The charge transfer channels include electrode pairs, each of which is formed by a charge storage electrode and a potential barrier electrode which are arranged so that a charge storage electrode of one pair is connected to a potential barrier electrode of an adjacent pair, to receive the same clock pulse.

Abstract: A mail processing apparatus feeds mail articles one by one, along a transport path. A stamp detecting device is disposed along the path to detect a stamp on the mail article. The stamp detecting device includes a light source for radiating ultraviolet light towards both sides of the mail article in the transport path, and converters for converting the luminescences excited by the ultraviolet light on both sides of the mail article. Two signal levels are detected and compared for determining where the stamp is located. This way, a stamp does not appear to be on both sides of a very thin article.

Abstract: A memory circuit having an improved address decoder which is operable with a low power consumption and can be fabricated at a high-integration is disclosed.The memory comprises a logic means for decoding a part of address signals provided for a plurality of address lines of a memory cell array, and a plurality of transfer gates provided between the logic means and the address lines, in which one of those transfer gates is made enabled in response to a different part of the address signals thereby to transmit the output signal of the logic means to a selected row line through the enabled transfer gate.

Abstract: A digital television special effect waveform generator produces a gate signal used for composing two video signals as a special effect, provided with a waveform having a soft width in which these two video signals are gradually alternated, according to the direct digital calculation of digital data consisting of a stating address, a central address and an aspect ratio of the waveform. As a result, a special effect waveform for smoothly alternating two video signals can be easily obtained with a comparatively simple digital circuit configuration prevented from the injurious influence of noise.

Abstract: A scan tracking apparatus for a helical scan tape recorder, comprising a movable tape head (11), a detector (13) detecting the envelope of the tape signal to produce a reproduced signal, sampling means (15) for sampling the reproduced signal at fixed points of the helical scan, memory (17) for storing the reproduced signal and correction signals from different tracks of the helical scan, computation means (2) for computing a correction signal to return the tape head to the center of the track, a sawtooth generator (2, 4) for producing a signal related to the tape speed (v), and a head driving mechanism (9) for moving the tape head in response to the sawtooth and correction signals.

Abstract: The ratio of gases during chemical vapor deposition of a silicon nitride layer in an MNOS Memory device is gradially varied during the deposition process to achieve a silicon nitride layer having a trap state distribution which gradually decreases from the oxide-nitride interface to the oxide-metal interface.

Abstract: In an encoding system comprising a buffer circuit for successively storing variable length codes and for producing the stored codes at a predetermined rate as transmission codes, a controller produces a control signal which stepwise specifies a variable amount of the stored codes. Responsive to the control signal, a preliminary processing circuit preliminarily processes the digital video signals into preliminarily processed signals which are dependent on the amounts and which are predictively encoded in accordance with an encoding rule by a non-recursive predictive encoder into predictive error signals with information of the preliminarily processed signals preserved. For use in the buffer circuit, a variable length encoder controlled by the control signal further encodes the predictive error signals into the variable length codes of code lengths related to the amounts. The processing circuit may comprise at least one of a quantizer, a thinning circuit, and a band compression circuit.

Abstract: An information handling apparatus comprises a memory storing a group of instructions. A memory location is designated where the instruction is to be read out of the memory. After a predetermined instruction has been read out, a signal is generated for inhibiting an execution of at least one subsequently scheduled instruction. After a short period of time, an address for a next new instruction is prepared. The new instruction is then read out in response to the prepared address. The instructions are regulated so that, although at least one portion of the instruction is read out of the memory by memory accessing, the processing defined by the instruction is not immediately executed. Typically, one such instruction may be followed by an instruction to subsequently skip an instruction.

Abstract: A printer head, for an ink-on-demand type ink-jet printer, squirts ink droplets onto a printing medium. The printer head includes a nozzle for delivering the ink droplets and a passage for supplying ink from an ink tank. The ink is pressurized in accordance with an electric signal which commands the delivery of the ink droplets. Fluid control valves are deformed under the action of the ink pressure.

Abstract: In a TDMA network wherein a central station sends signals towards satellite stations in downward frames (A), each comprising a control time slot (Td0) and speech time slots (Td1 to TdM), and receives signals from one to M satellite stations in upward frames (C) of a like format, the central station checks the number of idle time slots in each of the downward and upward frames. Only when the number exceeds a preselected number, one of the idle time slots is selected as an adjustment time slot. The ordinary number given to the adjustment time slot is transmitted in a number field (Nf) of the downward control time slot. Each satellite station generates a time axis indicative of local time slots (D) with a delay relative to the thereby received downward time slots (B). On adjusting the time axis in a selected satellite station, the station sends a short burst (t.sub.s) in the local time slot indicated by the received number field.

Abstract: A loudspeaking telephone system has a voice switch circuit in which voice signals on transmission and reception speech channels are respectively detected to produce control signals, and these control signals are compared to judge the levels of the voice signals on both the speech channels so that the switching between both the channels is effected under the control of loss of variable attenuators inserted in both the speech channels. The control signals corresponding to the voice signals on both the transmission and reception speech channels are converted through analog-to-digital conversion into digital values which are suitable for arithmetic operation. The arithmetic operation is such that the losses of the variable attenuators are automatically controlled in accordance with the use conditions of the loudspeaking telephone system to minimum values which can prevent the howling, transmitting blocking and receiving blocking.

Abstract: The incoming radar signals to a constant false alarm rate (CFAR) processor, having some known cumulative distribution function F(X) or probability density function f(X), are transformed into new signals Y according to the equationY=.sigma.[-1n {1-F.sub.x (X)}].sup.1/Kwhere .sigma. and K are a scale parameter and shape parameter, respectively, and can be arbitrarily set. The threshold to which the processed signal is compared in the CFAR processing is variable in accordance with the selected value of K.

Abstract: A system for recognizing a continuously spoken word sequence with reference to preselected reference words with the problem of coarticulation removed, comprises a pattern memory for memorizing demi-word pair reference patterns consisting of a former and a latter reference pattern segment for each reference word and a word pair reference pattern segment for each permutation with repetition of two words selected from the preselected reference words. A recognition unit is operable as a finite-state automaton on concatenating the demi-word pair reference patterns so that no contradiction occurs at each interface of the reference patterns in every concatenation. It is possible to use the automaton in restricting the number of reference patterns in each concatenation either to an odd or an even positive integer.

Abstract: A television synchronizing signal amplitude detection circuit for detecting the amplitude of composite television signals wherein the period of detection is determined by the vertical synchronizing signal interval including a vertical synchronizing pulse period and an equalizing pulse period preceding and succeeding the vertical synchronizing pulse period.

Abstract: A voltage comparator circuit which can operate stably without being affected by in-phase noise and can be fabricated with a small number of circuit elements is disclosed. The comparator circuit comprises a differential amplifier having a pair of input transistors of a first conductivity type, a latch circuit having a pair of latch transistors of a second conductivity type whose gates and drains are cross-coupled at a pair of output terminals of the differential amplifier, and means for controlling a potential at commonly connected source of the latch transistors.

Abstract: A character recognition system is disclosed in which an input character is compared to a plurality of standard characters. Each standard character is stored with respect to its black meshes in a first character memory area, and with respect to its white meshes in a second character memory area. The characters are stored in parallel such that one "row" of the memory corresponds to the same mesh area of each character. The input character is stored in a third memory area in terms of either its white or its black meshes. Means are provided which produce the address of the character memory area row which corresponds to an address of a mesh bit within the input character memory. The row is sequentially read out, and a counter is provided for each character. These counters are initiated when logical 1's are present in both the particular input character memory mesh bit and the corresponding character memory area bit. The outputs of the counters are cumulatively stored and compared.

Abstract: The present invention relates to a single-ended push-pull type inverter. Such inverter in the prior art generated a large through-current flowing through series-connected output transistors. This large through-current caused not only a large power consumption but also an instability of the entire circuit including the inverter. The present invention improves these disadvantages by inserting a phase inverter stage having a current regulating function just before the output transistors and includes a first transistor having a base receiving an input signal, the phase inverter stage having an input end connected to the collector of the first transistor, a second and a third transistor connected in series, the bases of the second and third transistors being electrically connected, respectively, to the collector of the first transistor and output end of the phase inverter stage and an output terminal connected to the circuit portion connecting the second and third transistors.