Abstract: New methods of filling gaps with dielectric material are provided. The methods involve plasma-enhanced chemical vapor deposition (PECVD) of a flowable polymerized film in a gap, followed by an in-situ treatment to convert the film to a dielectric material. According to various embodiments, the in-situ treatment may be a purely thermal or plasma treatment process. Unlike conventional PECVD processes of solid material, which deposit film in a conformal process, the deposition results in bottom-up fill of the gap. In certain embodiments, a deposition-in situ treatment-deposition-in situ treatment process is performed to form dielectric layers in the gap. The sequence is repeated as necessary for bottom up fill of the gap. Also in certain embodiments, an ex-situ post-treatment process is performed after gap fill is completed. The processes are applicable to frontend and backend gapfill.

Abstract: Methods of producing low resistivity tungsten bulk layers having lower roughness and higher reflectivity are provided. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. The methods involve CVD deposition of tungsten in the presence of alternating nitrogen gas pulses, such that alternating portions of the film are deposited by CVD in the absence of nitrogen and in the presence of nitrogen. According to various embodiments, between 20-90% of the total film thickness is deposited by CVD in the presence of nitrogen.

Abstract: Systems and methods include supplying process gas to a processing chamber including a substrate. Plasma is created in the processing chamber. After performing a first substrate processing step, the plasma is maintained in the processing chamber and at least one operating parameter is adjusted. The operating parameters may include RF bias to a pedestal, a plasma voltage bias, a gas admixture, a gas flow, a gas pressure, an etch to deposition (E/D) ratio and/or combinations thereof. One or more additional substrate processing steps are performed without an interruption in the plasma between the first substrate processing step and the one or more additional substrate processing steps.

Abstract: An apparatus for electroplating a layer of metal onto a work piece surface includes a membrane separating the chamber of the apparatus into a catholyte chamber and an anolyte chamber. In the catholyte chamber is a catholyte manifold region that includes a catholyte manifold and at least one flow distribution tube. The catholyte manifold and at least one flow distribution tube serve to mix and direct catholyte flow in the catholyte chamber. The provided configuration effectively reduces failure and improves the operational ranges of the apparatus.

Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: An apparatus for wet etching metal from a semiconductor wafer comprises a wafer holder for rotating a wafer and a plurality of nozzles for applying separate flow patterns of etching liquid to the surface of the wafer. The flow patterns impact the wafer in distinct band-like impact zones. The flow pattern of etching liquid from at least one nozzle is modulated during a total etching time control the cumulative etching rate in one local etch region relative to the cumulative etching rate in one or more other local etch regions. Some embodiments include a lower etch chamber and an upper rinse chamber separated by a horizontal splash shield. Some embodiments include a retractable vertical splash shield used to prevent splashing of etching liquid onto the inside walls of a treatment container. An etch-liquid delivery system includes a plurality of nozzle flow paths having corresponding nozzle flow resistances, and a plurality of drain flow paths having corresponding drain flow resistances.

Abstract: Systems and methods for processing a substrate include supplying steam in a chamber, arranging a substrate with a deposited layer that includes silicon in the chamber, and directing UV light onto the deposited layer in the presence of the steam for a predetermined conversion period to at least partially convert the deposited layer. Systems and methods for densifying a deposited layer of a substrate include supplying ammonia in a chamber, arranging the substrate that includes the deposited layer in the chamber, and directing UV light onto the deposited layer in the presence of the ammonia for a predetermined conversion period to at least partially densify the deposited layer.

Abstract: A substrate processing system includes one or more processing chambers defining N reaction volumes. N-1 first valves are arranged between the N reaction volumes. A controller communicates with the N-1 first valves and is configured to pressurize a first one of the N reaction volumes with precursor gas to a first target pressure, wait a first predetermined soak period, evacuate a second one of the N reaction volumes to a second target pressure that is lower than the first target pressure, and open one of the N-1 first valves between the first one of the N reaction volumes and a second one of the N reaction volumes.

Abstract: Embodiments related to depositing thin conformal films using plasma-activated conformal film deposition (CFD) processes are described herein. In one example, a method of processing a substrate includes, applying photoresist to the substrate, exposing the photoresist to light via a stepper, patterning the resist with a pattern and transferring the pattern to the substrate, selectively removing photoresist from the substrate, placing the substrate into a process station, and, in the process station, in a first phase, generating radicals off of the substrate and adsorbing the radicals to the substrate to form active species, in a first purge phase, purging the process station, in a second phase, supplying a reactive plasma to the surface, the reactive plasma configured to react with the active species and generate the film, and in a second purge phase, purging the process station.

Abstract: An apparatus for purging a space in a processing chamber comprises a source of a purge gas; an inlet portion of a purge ring; an inlet baffle located in the inlet portion and fluidically connected to the source of purge gas; and an exhaust portion of the purge ring. The inlet portion and the exhaust portion define a ring hole space having a 360° periphery. The inlet baffle preferably surrounds not less than 180° of said periphery. The inlet baffle is operable to convey purge gas into the ring hole space. The exhaust portion is operable to convey purge gas and other matter out of the ring hole space. Cleaning of the purge ring and other structures in a processing chamber is conducted by flowing a cleaning gas through the inlet baffle. Some embodiments include a gas inlet plenum and an exhaust channel but not a purge ring.

Abstract: Disclosed are methods of depositing a copper seed layer to be used for subsequent electroplating a bulk-layer of copper thereon. A copper seed layer may be deposited with different processes, including CVD, PVD, and electroplating. With electroplating methods for depositing a copper seed layer, disclosed are methods for depositing a copper alloy seed layer, methods for depositing a copper seed layer on the semi-noble metal layer with a non-corrosive electrolyte, methods of treating the semi-noble metal layer that the copper seed layer is deposited on, and methods for promoting a more uniform copper seed layer deposition across a semiconductor wafer.

Abstract: Disclosed are apparatus and methods for monitoring an operation parameter of a process tool, independently of a process system recipe, are provided. In one embodiment, the behavior of a process device as it transitions between different states is monitored for a single cycle of operation or over time to detect trends that indicate a potential failure of the process device. When a trend that indicates a potential failure is detected, an alarm is generated. In one implementation, the time for reaching a particular stage of operation may be repeatedly monitored over a plurality of device cycles. For example, the time to open a valve or door may be monitored. In another example, the time for reaching a stable phase of gas flow after a ramping stage has commenced is monitored. When the time for reaching a particular stage begins to decline by a predetermined amount, an alarm may be generated.

Abstract: A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Cascaded ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. Successive UV radiation of equal or shorter wavelengths with variable intensity and duration selectively breaks bonds in the Si—N matrix and minimizes shrinkage and film relaxation. Higher tensile stress than a non-cascaded approach may be obtained.

Abstract: A method of depositing a film on a substrate surface includes providing a substrate in a reaction chamber; selecting a silicon-containing reactant from a precursor group consisting of di-tert-butyl diazidosilane, bis(ethylmethylamido)silane, bis(diisopropylamino)silane, bis(tert-butylhydrazido)diethylsilane, tris(dimethylamido) silylazide, tris(dimethylamido)silylamide, ethylsilicon triazide, diisopropylaminosilane, and hexakis(dimethylamido)disilazane; introducing the silicon-containing reactant in vapor phase into the reaction chamber under conditions allowing the silicon-containing reactant to adsorb onto the substrate surface; introducing a second reactant in vapor phase into the reaction chamber while the silicon-containing reactant is adsorbed on the substrate surface, and wherein the second reactant is introduced without first sweeping the silicon-containing reactant out of the reaction chamber; and exposing the substrate surface to plasma to drive a reaction between the silicon-containing reactant and

Abstract: A plating protocol is employed to control plating of metal onto a wafer comprising a conductive seed layer. Initially, the protocol employs cathodic protection as the wafer is immersed in the plating solution. In certain embodiments, the current density of the wafer is constant during immersion. In a specific example, potentiostatic control is employed to produce a current density in the range of about 1.5 to 20 mA/cm2. The immersion step is followed by a high current pulse step. During bottom up fill inside the features of the wafer, a constant current or a current with a micropulse may be used. This protocol may protect the seed from corrosion while enhancing nucleation during the initial stages of plating.

Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.

Abstract: Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.

Abstract: Provided are apparatuses and methods disclosed for wafer processing. Specific embodiments include dual wafer handling systems that transfer wafers from storage cassettes to processing modules and back and aspects thereof. Stacked independent loadlocks that allow venting and pumping operations to work in parallel and may be optimized for particle reduction are provided. Also provided are annular designs for radial top down flow during loadlock vent and pumpdown.

Abstract: Methods correcting wafer position error are provided. The methods involve measuring wafer position error on a robot during transfer to an intermediate station. This measurement data is then used by a second robot to perform wafer pick moves from the intermediate station with corrections to center the wafer. Wafer position correction may be performed at only one location during the transfer process. Also provided are systems and apparatuses for transferring wafers using an intermediate station.

Abstract: A method of forming a boron nitride or boron carbon nitride dielectric produces a conformal layer without loading effect. The dielectric layer is formed by chemical vapor deposition (CVD) of a boron-containing film on a substrate, at least a portion of the deposition being conducted without plasma, and then exposing the deposited boron-containing film to a plasma. The CVD component dominates the deposition process, producing a conformal film without loading effect. The dielectric is ashable, and can be removed with a hydrogen plasma without impacting surrounding materials. The dielectric has a much lower wet etch rate compared to other front end spacer or hard mask materials such as silicon oxide or silicon nitride, and has a relatively low dielectric constant, much lower then silicon nitride.