Abstract: Technology is provided for distributed power delivery to a processing unit on a printed circuit board. In one example, a printed circuit board includes a processing unit coupled to multiple power channels, including first channels on a first side of the processing unit, and second channels on a second side of the processing unit. The printed circuit board further includes a first power supply coupled to the processing unit via the first channels, and a second power supply coupled to the processing unit via the second channels. The processing unit is configured to receive a total current, including currents drawn substantially simultaneously from the first power supply and the second power supply. The total current is about equivalent to a current the processing unit would draw from a single power supply.

Abstract: A method for correcting a shift error in a fused multiply add operation. The method comprises adjusting a normalized floating-point number before performing a shift error correction to produce an adjusted normalized floating-point number, and correcting a shift error in the adjusted normalized floating-point number. The correcting the shift error comprises shifting a mantissa of the adjusted normalized floating-point number in one direction. A fused multiply add module comprising a normalizer module, a compensation logic, and a round. The normalizer module is operable to normalize a floating-point number to produce a normalized floating-point number. The floating-point number is normalized based upon an estimated quantity of leading zeros. The compensation logic is operable to manage a correction of a shift error in the normalized floating-point number. The rounder is operable to correct the shift error with a mantissa shift in only one direction.

Abstract: Circuits, methods, and apparatus that provide parallel execution relationships to be included in a function call or other appropriate portion of a command or instruction in a sequential programming language. One example provides a token-based method of expressing parallel execution relationships. Each process that can be executed in parallel is given a separate token. Later processes that depend on earlier processes wait to receive the appropriate token before being executed. In another example, counters are used in place to tokens to determine when a process is completed. Each function is a number of individual functions or threads, where each thread performs the same operation on a different piece of data. A counter is used to track the number of threads that have been executed. When each thread in the function has been executed, a later function that relies on data generated by the earlier function may be executed.

Abstract: A decision feedback equalizer system is disclosed. The decision feedback equalizer system includes a current summer core that in current mode, removes inter-symbol interference from a signal, and, a CMOS latch component, that is coupled to the current summer core, that receives a current mode signal and outputs a CMOS compatible signal. The components of the decision feedback equalizer system are controlled by a single clock.

Abstract: A method includes querying, through a processor, a database of color profiles to determine a secondary color profile therefrom, and comparing, through the processor, the determined secondary color profile to a primary color profile of a primary display communicatively coupled to the processor. The method also includes selecting, through the processor, the determined secondary color profile to be applied to a secondary display also communicatively coupled to the processor upon determining that multimedia content displayed on the primary display with the primary color profile matches with the same multimedia content displayed on the secondary display with the determined secondary color profile. Further, the method includes reducing a color discrepancy between the same multimedia content on the primary display and the secondary display based on rendering the same multimedia content on the primary display with the primary color profile and the secondary display with the selected secondary color profile.

Abstract: One embodiment of the present invention sets forth a technique for rendering paths by first generating a stencil buffer indicating pixels of the path that should be covered and then covering the path. The paths may be filled or stroked without tessellating the paths. Path rendering may be accelerated when a graphics processing unit or other processor that is configured to perform operations to generate the stencil buffer and cover the path to fill or stroke the path. When the paths are rendered in a top-to-bottom (front-to-back) order, an opacity stencil may be generated and used to avoid determining path coverage and shading for pixels that are opaque.

Abstract: The server based graphics processing techniques, describer herein, include passing graphics commands from a shim layer to a guest display device interface, wherein the shim layer and the guest display device interface (DDI) are executing in a given instance of a guest virtual machine (VM). The guest DDI calls back to the shim layer with corresponding function calls. The function calls are passed from the shim layer to a host DDI through a communication channel of a host-guest communication manager (HGCM), wherein the host display device interface and host-guest communication manager are executing in a host virtual machine manager (VMM).

Abstract: One embodiment of the present invention sets forth a technique for improved rasterization of round points mapped into a tile space within a graphics processing pipeline. A set of candidate tiles are selected based on proximity to a round point. A tile within the set of candidate tiles may be rejected based on a rejection boundary. A tile may be rejected if no vertex associated with the tile is within the coverage area. Performance is improved by rejecting certain unneeded tiles that would otherwise be included in conventional rasterization. One embodiment advantageously enlists line drawing circuitry to determine whether a given tile intersects the coverage area.

Abstract: A graphics processing system configured to track per-tile event counts in a tile-based architecture. A tiling unit in the graphics processing system is configured to cause a screen-space pipeline to load a count value associated with a first cache tile into a count memory and to cause the screen-space pipeline to process a first set of primitives that intersect the first cache tile. The tiling unit is further configured to cause the screen-space pipeline to store a second count value in a report memory location. The tiling unit is also configured to cause the screen-space pipeline to process a second set of primitives that intersect the first cache tile and to cause the screen-space pipeline to store a third count value in the first accumulating memory. Conditional rendering operations may be performed on a per-cache tile basis, based on the per-tile event count.

Abstract: A clock signal generation circuit provides an output clock signal to a digital system. The digital system is powered by a power supply voltage, VDD, that may include transients associated with the impedance of the packaged digital system. The clock signal generation circuit dynamically scales an output clock frequency based on monitored changed to VDD. The output clock frequency may be selected to approximate a maximum (margin-less) system Fmax for the monitored VDD. The average clock frequency may be improved compared with operating at a fixed output clock frequency.

Abstract: A clock frequency controller for a processor and a method of operation thereof. The clock frequency controller may be embodied in a processor, including: (1) a processing core operable at a clock frequency to undertake a processing of a graphics application, and (2) a clock frequency controller coupled to the processing core and operable to adjust the clock frequency based on a current frame rate of the processing and a target frame rate for the processing.

Abstract: One embodiment of the present invention sets forth a technique for rendering paths by first generating a stencil buffer indicating pixels of the path that should be covered and then covering the path. The paths may be filled or stroked without tessellating the paths. Path rendering may be accelerated when a graphics processing unit or other processor that is configured to perform operations to generate the stencil buffer and cover the path to fill or stroke the path.

Abstract: Embodiments of the present invention are directed to methods and systems for robust weighting of gray patches in automatic white balancing in an image-capture device by utilizing kernel density estimation techniques with dynamically variable bandwidth to determine the probability density of samples to create an initial estimate, then verifying the initial gray point estimate to account for outliers. In one embodiment, given a set of image data, an initial gray point estimate in a color space is determined for the set of image data. The initial estimate is then refined by weighting the sub-population with the greatest probability of being gray. A final evaluation that includes a further comparison to pre-programmed constraints determines a final estimate, which can still be further tuned according to user preferences by adjusting color biases. The resulting final gray point estimate provides greater stability, and greatly improved accuracy over traditional techniques and solutions.

Abstract: Techniques are disclosed for tracing a ray within a parallel processing unit. A first thread receives a ray or a ray segment for tracing and identifies a first node within an acceleration structure associated with the ray, where the first node is associated with a volume of space traversed by the ray. The thread identifies the child nodes of the first node, where each child node is associated with a different sub-volume of space, and each sub-volume is associated with a corresponding ray segment. The thread determines that two or more nodes are associated with sub-volumes of space that intersect the ray segment. The thread selects one of these nodes for processing by the first thread and another for processing by a second thread. One advantage of the disclosed technique is that the threads in a thread group perform ray tracing more efficiently in that idle time is reduced.

Abstract: Embodiments of the present invention set forth a technique for optimizing the performance and efficiency of complex, software-based computations, such as lighting computations. Data entering a graphics application programming interface (API) in a conventional arithmetic representation, such as floating-point or fixed-point, is converted to an internal logarithmic representation for greater computational efficiency. Lighting computations are then performed using logarithmic space arithmetic routines that, on average, execute more efficiently than similar routines performed in a native floating-point format. The lighting computation results, represented as logarithmic space numbers, are converted back to floating-point numbers before being transmitted to a graphics processing unit (GPU) for further processing. Because of efficiencies of logarithmic space arithmetic, performance improvements may be realized relative to prior art approaches to performing software-based floating-point operations.

Abstract: Embodiments of the present invention are directed to methods and a system that allow for deterministic parallel low discrepancy sampling, which can be efficiently processed, and are effective in removing transitionary artifacts that occur in low-dimensional projections generated in low discrepancy sequences. Embodiments of the claimed subject matter further provide improvements upon the low-dimensional projections and thus the visual quality when using the Sobol' sequence for image synthesis.

Abstract: A system, method, and computer program product are provided for tiled deferred shading. In operation, a plurality of photons associated with at least one scene are identified. Further, a plurality of screen-space tiles associated with the at least one scene are identified. Additionally, each of the plurality of screen-space tiles capable of being affected by a projection of an effect sphere for each of the plurality of photons are identified. Furthermore, at least a subset of photons associated with each of the screen-space tiles from which to compute shading are selected. Moreover, shading for the at least one scene is computed utilizing the selected at least a subset of photons.

Abstract: A system, method, and computer program product are provided for using a bit-count texture format. A rasterized coverage bit mask is received by a texture processing unit from a bit-count format texture map, the rasterized coverage bit mask is converted to a scalar value, and the scalar value is processed while the rasterized coverage bit mask is retained in the bit-count format texture map. The coverage bit mask may be converted by computing a count of samples that are covered by at least one graphics primitive according to the rasterized coverage bit mask.

Abstract: A method for filtering a data signal includes transmitting the data signal from a transmitter to a receiver across a conductor disposed in an interposer, which interconnects the receiver and the transmitter. The data signal is low-passed with a filter, which includes a passive resistive element disposed within the interposer and coupled in series electrically with a passive inductive element. In relation thereto, the interposer is disposed in a position within the interposer, or upon a surface thereof. The filter is coupled to the conductor in a shunt configuration with respect to ground.

Abstract: An embodiment of a computing system is configured to process data using a multithreaded SIMD architecture that includes heterogeneous processing engines to execute a program. The program is constructed of various program instructions. A first type of the program instructions can only be executed by a first type of processing engine and a second type of program instructions can only be executed by a second type of processing engine. A third type of program instructions can be executed by the first and the second type of processing engines. An instruction dispatcher is configured to identify and remove program instruction execution conflicts for the heterogeneous processing engines to improve instruction execution throughput.