Abstract: A method and system for protecting content in graphics memory are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of storing a first privilege level in a privilege map with restricted access, wherein the first privilege level is associated with a memory page used to store the content; and determining whether to permit a request to access the memory page based on the first privilege level.

Abstract: Scalable techniques for dynamic data encoding and decoding are directed toward a system including a plurality of frame processing units. A main frame processing unit manages frame processing unit resource, dispatches frames to appropriate frame processing units. One or more auxiliary frame processing units encode or decode the non-reference frames dispatched by the main frame processing unit. The main frame processing unit encodes or decodes the reference frames and encodes or decodes non-reference frames if none of the auxiliary frame processing units are available.

Abstract: In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

Abstract: A method includes predicting, through a processor of a data processing device communicatively coupled to a memory, a portion of a video frame on which a user of the data processing device is likely to focus on during rendering thereof on a display unit associated with the data processing device. The video frame is part of decoded video data. The method also includes rendering, through the processor, the portion of the video frame on the display unit at an enhanced level compared to other portions thereof following the prediction of the portion of the video frame.

Abstract: A system for driving a plurality of loads each connected to respective signal terminals and to a shared common load terminal. Multiple conventional signal amplifiers each provide a content signal at one of the signal terminals. The signal amplifiers each have a primary-power upper terminal, to receive a first voltage (V1) from a first power supply, and a primary-power lower terminal, to receive a second voltage (V2) from the first power supply. A bias amplifier biases the common load terminal, and has a secondary-power upper terminal to receive a third voltage (V3) from a second power supply and a secondary-power lower terminal to receive a fourth voltage (V4) from the second power supply, wherein V2?V4<V3?V1.

Abstract: A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.

Abstract: A system, method, and computer program product are provided for changing a state of operation of a display system with respect to at least a portion of an image occluded by a non-display surface. In use, a display system is operated in a first state associated with an occlusion of at least a portion of an image resulting from a non-display surface associated with the display system. Additionally, independent of a control panel user interface, a command is received to operate the display system in a second state associated with the occlusion of the at least a portion of the image resulting from the non-display surface associated with the display system. Furthermore, in response to the command, the display system is operated in the second state associated with the occlusion of the at least a portion of the image resulting from the non-display surface associated with the display system.

Abstract: Disclosed are methods and systems to reduce voltage noise on a printed circuit board (PCB) through a co-layout of multilayer ceramic capacitors. In one or more embodiments, this surface mounted layout comprises a first co-layout of multilayer ceramic capacitors mounted on a first corner of a rectangular footprint of a bottom side of the PCB; a second co-layout of multilayer ceramic capacitors mounted on a second corner of the rectangular footprint diagonal to the first corner; and a first solid electrolytic polymer capacitor and a second solid electrolytic polymer capacitor mounted on the remaining corners, respectively, of the rectangular footprint. The rectangular footprint of the PCB is a footprint of a high-speed processing unit mounted on the PCB. The high-speed processing unit is mounted on a top side of the PCB opposite the bottom side comprising the first co-layout of multilayer ceramic capacitors and the second co-layout of multilayer ceramic capacitors.

Abstract: One embodiment of the present invention sets forth a technique for generating and transmitting video frame data from a graphics processing unit (GPU) to a color field sequential display device capable of displaying an auto-stereoscopic image. A frame buffer image comprising per-pixel packed color channels is transformed to a frame buffer image comprising regions corresponding to the color channels with vertical blanking regions inserted between color sub-field regions. Each region of the transformed frame buffer image is sequentially transmitted to the color field sequential display device for display of the corresponding color channel. Backlight illumination for each color channel is controlled by the GPU for temporal alignment with display of each color channel during the vertical blanking interval. The technique is compatible with lenticular and parallax barrier displays.

Abstract: A system, method, and computer program product are provided for enhancing an image utilizing a hyper-clarity transform. In use, an image is identified. Additionally, the identified image is enhanced, utilizing a hyper-clarity transform. Further, the enhanced image is returned.

Abstract: This document discusses systems and methods that track overall time for processing operations such that the processing time can be shared among the resources efficiently. Processing time can be shifted to image processing to provide the most benefit to image quality. Moreover, access time from one process is banked to be used by a subsequent process or on a subsequent group of pixels. This document discusses systems and methods that provide additional processing power on an as needed basis. For example, a processing stage and its controller are outside the normal pixel processing flow path. When it is determined that additional processing is required, the processing stage and its controller are activated to perform the additional processing. This document discusses systems and methods that provide parallel processing in a processing stage such that the data can flow internal to the controller linked to the processing stage and globally.

Abstract: A solution is proposed to perform display updates in a lower power user interface. According to one embodiment, the display panel is placed in the lower possible refresh rate that can be supported. Rendered updates are presented to the displays at the fasted possible pixel rates the communication interface between the rendering component to the display panel can support, and a buffer on the receiving end of the display receives and stores updated frames as they are rendered and transmitted. Subsequent display updates (generated in response to subsequent sensor input, for example) may be created and transmitted as soon as the preceding display frames are buffered. In the meantime, as soon as the update frame is transmitted, the timing controller of the display panel is instructed to interrupt the current refresh period and to immediately rescan the frame.

Abstract: A system and method are provided for regulating a supply voltage of a device. The method includes the steps of determining whether a supply voltage for an analog multiplexor is below a threshold voltage. If the supply voltage for the analog multiplexor is below the threshold voltage, then the method includes the step of shorting the supply voltage to an output of the analog multiplexor. However, if the supply voltage for the analog multiplexor is above or equal to the threshold voltage, then the method includes the step of transmitting at least one input signal coupled to the analog multiplexor to the output of the analog multiplexor. A system configured to implement the method may include a power management integrated circuit configured to generate a supply voltage for a device and a device that includes a self-powered analog multiplexor with voltage sensing bypass switch.

Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.

Abstract: Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control dependence on a block that is either divergent or comprising a variant branch condition. Convergent basic blocks that are defined by invariant instructions are advantageously identified as candidates for scalarization by a thread program compiler.

Abstract: A system, method, and computer program product are provided for debugging graphics programs via a system with a single graphics processing unit. The method includes the steps of storing an initial state of an application programming interface context in a memory, intercepting a stream of API commands associated with the frame, transmitting the stream of API commands to a software layer that implements the API to render the frame, and in response to a breakpoint, storing a graphics processing unit context in the memory. The initial state of the API context corresponds to the start of a frame, and the stream of API commands are generated by a graphics application.

Abstract: A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal. A downstream valid signal is generated by the first pipeline stage based on an upstream valid signal and the delayed ready signal. An upstream ready signal is generated by the first pipeline stage based on the delayed ready signal and the downstream valid signal.

Abstract: A method includes identifying a divergent region of interest (DRI) not including a post dominator node thereof within a control flow graph, and introducing a decision node in the control flow graph such that the decision node post-dominates an entry point of the DRI and is dominated by the entry point. The method also includes redirecting a regular control flow path within the control flow graph from another node previously coupled to the DRI to the decision node, and redirecting a runaway path from the another node to the decision node. Further, the method includes marking the runaway path to differentiate the runaway path from the regular control flow path, and directing control flow from the decision node to an originally intended destination of each of the regular control flow path and the runaway path based on the marking to provide for program thread synchronization and optimization within the DRI.

Abstract: One embodiment of the present invention sets forth a technique for controlling mode switches in hardware. The resource manager includes an “is mode possible” function that evaluates a given mode in conjunction with the limitations of the hardware to determine if the given mode is feasible. The display driver is configured to call this function to validate a proposed mode before generating commands specifying the state changes for the display heads. The display software interface hardware module within the GPU processes these commands and follows a standard sequence of steps to implement the mode switch. The steps may include interrupts to the resource manager to re-validate the proposed mode, again calling the “is mode possible” function, or perform operations that are not yet supported in the hardware. Advantageously, controlling mode switches in hardware enables less error-prone, more efficient, and more discerning mode switches relative to controlling mode switches in software.

Abstract: A test system and method for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics in a wafer fabrication process. In one embodiment, the test system includes: (1) structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies over integrated circuit (IC) samples fabricated under different process conditions and (2) derating factor selection circuitry coupled to the structural at-speed ATE and configured to employ results of the structural at-speed tests to identify performance deterioration in the samples, the performance deterioration indicating the derating factor to be employed in a subsequent wafer fabrication process.