Abstract: A system, method, and computer program product for management of dynamic task-dependency graphs. The method includes the steps of generating a first task data structure in a memory for a first task, generating a second task data structure in the memory, storing a pointer to the second task data structure in a first output dependence field of the first task data structure, setting a reference counter field of the second task data structure to a threshold value that indicates a number of dependent events associated with the second task, and launching the second task when the reference counter field stores a particular value. The second task data structure is a placeholder for a second task that is dependent on the first task.

Abstract: A system and method for launching data parallel and task parallel application threads. In one embodiment, the system includes: (1) a global thread launcher operable to retrieve a launch request from a queue and track buffer resources associated with the launch request and allocate output buffers therefor and (2) a local thread launcher associated with a streaming multiprocessor and operable to receive the launch request from the global thread launcher, set a program counter and resource pointers of pipelines of the streaming multiprocessor and receive reports from pipelines thereof as threads complete execution.

Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and is analyzed to identify subsets of samples of a multi-sample pixel that have equal data, such that data for one sample in a subset represents multi-sample pixel data for all samples in the subset. An encoding state is generated that indicates which samples of the multi-sample pixel are included in each one of the subsets.

Abstract: Embodiments are disclosed relating to an electric power conversion device and methods for controlling the operation thereof. One disclosed embodiment provides an electric power conversion device comprising a first current control mechanism coupled to an electric power source and an upstream end of an inductor, where the first current control mechanism is operable to control inductor current. The electric power conversion device further comprises a second current control mechanism coupled between the downstream end of the inductor and a load, where the second current control mechanism is operable to control how much of the inductor current is delivered to the load.

Abstract: A system, method, and computer program product are provided for determining settings for a device. In use, a plurality of parameters associated with a device is identified. Additionally, one or more settings associated with the device are determined, based on the plurality of parameters.

Abstract: A computer-implemented method for drawing graphical objects within a graphics processing pipeline is disclosed. The method includes determining that a bypass mode for a first primitive is a no-bypass mode. The method further includes rasterizing the first primitive to generate a first set of rasterization results. The method further includes generating a first set of colors for the first set of rasterization results via a pixel shader unit. The method further includes rasterizing a second primitive to generate a second set of rasterization results. The method further includes generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any processing operations on the second set of rasterization results. The method further includes transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further processing.

Abstract: The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the client subsystems. Similarly, data associated with write data requests is transmitted from the client subsystems to the cache memory. To allow for the transmission of both read and write data on the crossbar unit, an arbiter is configured to schedule the crossbar unit transmissions as well and arbitrate between data requests received from the client subsystems.

Abstract: A multiplexer tree operable to control an output a sequence of data stored in a plurality of storage units in accordance with a non-linear address sequence that has less bit transition counts than a linear address sequence. The non-linear address sequence is provided to the selection inputs of the multiplexer tree and causes the levels having greater numbers of multiplexers to toggle less frequently than the levels having smaller numbers of multiplexers. The non-linear address sequence may comprise a Gray code sequence where every two adjacent addresses differ by a single bit. The non-linear address sequence may be optimized to minimize transistor switching in the multiplexer tree.

Abstract: A static read-only memory (SRAM) includes one or more bit cell rows that each includes a collection of bit cells. Each bit cell row is coupled to two or more different wordlines, where each wordline associated with a given bit cell row provides memory access to a different subset of bit cells within that bit cell row.

Abstract: Image scaling techniques, in accordance with embodiments of the present technology, include directionally interpolating blocks of pixel data of an image, sharpening the directional interpolated blocks of pixel data, and optionally clamping the sharpened, directional interpolated blocks of pixel data.

Abstract: One embodiment of the present invention sets forth a method for generating work to be processed by a graphics pipeline residing within a graphics processor. The method includes the steps of receiving an indication that a first graphics workload is to be submitted to a command queue associated with the graphics processor, allocating a first portion of shader accessible memory for one or more units of state information that are necessary for processing the first graphics workload, populating the first portion of shader accessible memory with the one or more units of state information, and transmitting to the command queue of the graphics processor the one or more units of state information stored within the first portion of shader accessible memory, wherein the first graphics workload is processed within the graphics pipeline based on the one or more units of state information.

Abstract: A system, method, and computer program product are provided for determining a monotonic set of presets. In use, a plurality of parameters associated with a product or service is identified. Additionally, a monotonic set of presets associated with the product or service are determined, based on the plurality of parameters.

Abstract: Banks within a dynamic random access memory (DRAM) are managed with virtual bank managers. A DRAM controller receives a new memory access request to DRAM including a plurality of banks. If the request accesses a location in DRAM where no virtual bank manager includes parameters for the corresponding DRAM page, then a virtual bank manager is allocated to the physical bank associated with the DRAM page. The bank manager is initialized to include parameters needed by the DRAM controller to access the DRAM page. The memory access request is then processed using the parameters associated with the virtual bank manager. One advantage of the disclosed technique is that the banks of a DRAM module are controlled with fewer bank managers than in previous DRAM controller designs. As a result, less surface area on the DRAM controller circuit is dedicated to bank managers.

Abstract: A system, method, and computer program product are provided for implementing asymmetric AES-CBC (Advanced Encryption Standard-Cipher Block Chaining) channels usage between encryption and decryption of data. In operation, data to be written to memory is identified. In addition, the data is encrypted utilizing a first AES-CBC channel. Additionally, at least one of a plurality of AES-CBC channels is utilized to decrypt the data to achieve a determined performance target.

Abstract: The present invention discloses a naked eye 3D video system for backing a vehicle and vehicles including the system. The naked eye 3D video system includes: two cameras for being installed on the rear of the vehicle and configured to capture images of the scene behind the vehicle respectively; a processor configured to divide the images captured by the two cameras into image strips in equidistance respectively, and integrate alternatively the divided image strips together into a integrated image in the manner of interleave; and a display device for being installed on the instrument panel of the vehicle, and configured to display the integrated image in the form of three dimensions for a driver to watch with the naked eye. The above naked eye 3D video system for backing a vehicle provided by the present invention can make the driver see clearly any obstacle in the scene behind the vehicle and understand spatial distribution information between the vehicle and the obstacle.

Abstract: In a touchscreen viewing device, a method for implementing a crease effect. The method includes receiving a swipe input related to an image displayed on a touch screen of a viewing device, upon determination that the swipe input will generate an item end effect, causing a crease effect to appear on the image in response to the swipe input, and subsequent to the end of the swipe input, undoing the crease effect on the image to return the image to an original effect.

Abstract: A compiler-controlled technique for scheduling threads to execute different regions of a program. A compiler analyzes program code to determine a control flow graph for the program code. The control flow graph contains regions and directed edges between regions. The regions have associated execution priorities. The directed edges indicate the direction of program control flow. Each region has a thread frontier which contains one or more regions. The compiler inserts one or more update predicate mask variable instructions at the end of a region. The compiler also inserts one or more conditional branch instructions at the end of the region. The conditional branch instructions are arranged in order of execution priority of the regions in the thread frontier of the region, to enforce execution priority of the regions at runtime.

Abstract: A message exchange system for software components on different processors. A first component's attempt to load a write register with a message pointer (or a message itself) triggers a determination whether space exists in a shared memory queue. If so, the queue is updated by incrementing a message counter, writing the message/pointer into the queue where designated by a write pointer, and changing the write pointer to a next queue location. A second component's attempt to load the message/pointer from a read register triggers a determination whether there is at least one new message in the queue. If so, the queue is updated by decrementing the message counter, reading the message/pointer from the queue where designated by a read pointer, and changing the read pointer to point to a next queue location. The determinations and queue updates are performed atomically with respect to the software components.

Abstract: A method includes providing an input port and/or an output port directly interfaced with a Graphics Processing Unit (GPU) of a data processing device further including a Central Processing Unit (CPU) to enable a corresponding reception of input data and/or rendering of output data therethrough. The method also includes implementing a voice/audio processing engine in the data processing device. Further, the method includes performing voice/audio related processing of the input data received through the input port and/or voice/audio related processing of data in the data processing device to realize the output data based on executing the voice/audio processing engine solely through the GPU.

Abstract: A system, method, and computer program product are provided for generating primitive-specific attributes. In operation, it is determined whether a portion of a graphics processor is operating in a predetermined mode. If it is determined that the portion of the graphics processor is operating in the predetermined mode, only one or more primitive-specific attributes are generated in association with a primitive.