Patents Assigned to NVidia
  • ADAPTIVE VIDEO COMPRESSION FOR LATENCY CONTROL
    Publication number: 20150103880
    Abstract: One embodiment of the present invention sets forth a technique for adaptively compressing video frames. The technique includes encoding a first plurality of video frames based on a first video compression algorithm to generate first encoded video frames and transmitting the first encoded video frames to a client device. The technique further includes receiving a user input event, switching from the first video compression algorithm to a second video compression algorithm in response to the user input event, encoding a second plurality of video frames based on the second video compression algorithm to generate second encoded video frames, and transmitting the second encoded video frames to the client device.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: NVIDIA CORPORATION
    Inventor: Franck R. DIARD
  • SYSTEMS AND METHODS TO LIMIT LAG BETWEEN A CLIENT AND A SERVER FOR REMOTE COMPUTING
    Publication number: 20150103894
    Abstract: Novel solutions are described herein for providing a consistent quality of service, latency-wise, for remote processing by managing the process queues in a processing server and temporarily pausing frame production and delivery to limit the lag experienced by a user in a client device. The claimed embodiments limit the latency (lag) experienced by a user by preventing the production rate of rendered frames at the server from significantly outperforming the decoding and display of the received frames in the client device and avoiding the resultant lag.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: NVIDIA CORPORATION
    Inventor: Franck DIARD
  • SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR GAMMA CORRECTION IN A VIDEO OR IMAGE PROCESSING ENGINE
    Publication number: 20150103252
    Abstract: A system and method are provided for generating a gamma adjusted value. The method comprises generating a logarithm space representation of an input value by computing a logarithm of the input value, computing a logarithm space gamma-adjusted value by multiplying the logarithm space representation with a current gamma value, and generating the gamma adjusted value by computing an antilogarithm of the logarithm space gamma-adjusted value.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: NVIDIA Corporation
    Inventors: Narendra Keshav Rane, Mukesh Chand Agarwal, Sandeep Vangipuram, Satinder Kumar
  • CONFIGURABLE DELAY CIRCUIT AND METHOD OF CLOCK BUFFERING
    Publication number: 20150103584
    Abstract: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: Nvidia Corporation
    Inventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
  • JITTER DETERMINATION OF NOISY ELECTRICAL SIGNALS
    Publication number: 20150102799
    Abstract: A jitter analysis system includes an electronic circuit having a noisy electrical signal with jitter along a baseline of the signal. The jitter analysis system also includes a sampling unit coupled to the noisy electrical signal that provides waveform samples of the noisy electrical timing signal and a jitter detection unit coupled to the sampling unit that provides baseline crossings of the noisy electrical signal, wherein the baseline crossings are determined from a selection of the waveform samples proximate the baseline of the signal. A jitter determination method is also provided.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: Nvidia Corporation
    Inventor: Hans Wolfgang Schulze
  • SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DISCARDING PIXEL SAMPLES
    Publication number: 20150103087
    Abstract: A system, method, and computer program product are provided for discarding pixel samples. The method includes the steps of completing shading operations for a pixel set including one or more pixels to generate per-sample shaded attributes according to a shader program executed by a processing pipeline. Discard information for the pixel set is evaluated and one or more per-sample shaded attributes for at least one pixel in the pixel set are discarded based on the evaluated discard information.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: NVIDIA Corporation
    Inventors: Christian Jean Rouet, Manan Maheshkumar Patel, Shirish Gadre, Daniel Paul Wilde
  • METHOD AND APPARATUS FOR LONG TERM IMAGE EXPOSURE WITH IMAGE STABILIZATION ON A MOBILE DEVICE
    Publication number: 20150103193
    Abstract: A method for displaying a live preview image on a mobile device is disclosed. The method comprises computing a history color value and confidence value for each pixel of a sensor of a camera on the device. Further, it comprises obtaining a new frame of pixels from the camera. Subsequently, for each pixel in the new frame, the method comprises: (a) determining if a pixel color is similar to a corresponding history color value and if a confidence corresponding to a pixel is above a predetermined threshold; (b) if the pixel color is not similar to the history color value and the confidence is above the predetermined threshold, displaying the history color value on the preview when displaying the new frame; and (c) if the pixel color is similar to the history color value or the confidence is below the threshold, displaying the pixel color on the preview instead.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 16, 2015
    Applicant: NVIDIA Corporation
    Inventors: Syed Zahir Bokari, Josh Abbott, Jim van Welzen
  • Energy-Based Control Of A Switching Regulator
    Publication number: 20150102788
    Abstract: A system and method are provided for controlling a switching voltage regulator circuit. An energy difference between a stored energy of a switching voltage regulator and a target energy is determined. A control variable of the switching voltage regulator is computed based on the energy difference and the control variable is applied to a current control mechanism of the switching voltage regulator. In one embodiment, the control variable is pulse width of a control signal.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: NVIDIA Corporation
    Inventor: William J. Dally
  • REMOTELY CONTROLLING ONE OR MORE DISPLAY UNIT(S) COMMUNICATIVELY COUPLED TO A DATA PROCESSING DEVICE AND/OR DISPLAY DATA RENDERED THEREON
    Publication number: 20150106729
    Abstract: A method includes executing a process on a data processing device, and defining, through a driver component, mapping between: the process and a display unit communicatively coupled to the data processing device, and one or more other processes executing on the data processing device and one or more other display unit(s) communicatively coupled to the data processing device. Based on the execution of the process on the data processing device, the method also includes providing a capability to: preview display data rendered on the one or more other display unit(s) through the display unit in a user interface provided through the process, and configure the display data rendered on the one or more other display unit(s) and/or one or more parameter(s) associated with the display data rendered on the one or more other display unit(s) and/or the one or more other display unit(s) directly through the preview.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: NVIDIA Corporation
    Inventor: Harsha Kumar
  • System and method for compensating measured IDDQ values
    Patent number: 9007079
    Abstract: An IDDQ test system and method that, in one embodiment, includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: April 14, 2015
    Assignee: Nvidia Corporation
    Inventors: Dushyant Narayen, Nerinder Singh, Gunaseelan Ponnuvel, Hemant Kumar, Luai Nasser, Craig Nishizaki
  • Flip-flop
    Patent number: 9007113
    Abstract: According to one aspect of the present disclosure, there is provided a flip flop circuit, comprising a first input circuit configured to receive a clock input signal and input data and comprising a first node. The flip-clop circuit further comprises a second input circuit configured to receive the input data and an inverse of the clock signal and comprising a second node. The first and second input circuits are configured such that the first node and the second node are pre-charged to respective complementary states when the clock signal is at a first level and, dependent on a value of the input data, one of said first and second nodes changes state to a state complementary to its pre-charged state when the clock signal transitions from the first level to a second level.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 14, 2015
    Assignee: NVIDIA Corporation
    Inventors: Stephen Felix, Stéphane Badel
  • Automatic loop-bandwidth calibration for a digital phased-locked loop
    Patent number: 9007109
    Abstract: A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: April 14, 2015
    Assignee: Nvidia Corporation
    Inventors: Seydou Ba, Abdellatif Bellaouar, Ahmed R Fridi
  • Texture map component optimization
    Patent number: 9007389
    Abstract: Embodiments of the present invention are directed towards increasing texture filtering performance for texel components represented by more than 8 bits. As the number of bits per component increases, the number of texels that are processed each clock cycle decreases since more bits need to be processed to produce each filtered result. A filtered result may be accumulated over two or more iterations, with each iteration producing a portion of the filtered result. When only a portion of the components for each texel are used, the unused texel components are not processed. Elimination of unnecessary texel processing for unused texel components may improve texture filtering performance.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: April 14, 2015
    Assignee: NVIDIA Corporation
    Inventor: Paul S. Heckbert
  • System and method for detecting errors in audio data
    Patent number: 9009561
    Abstract: An application programming interface (API) executed by a first processing unit combines audio data samples with error code values generated for those samples. The API then causes a data stream to be opened having sufficient bandwidth to accommodate combined samples made up of audio data samples and corresponding error code values. The combined samples are then transmitted to a decoder and validation unit within a second processing unit that receives the combined data, strips the error code values and validates the audio data based on the error code values. When the error code values indicate that the audio data has been compromised, the second processing unit terminates the output of sound derived from the audio data.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: April 14, 2015
    Assignee: NVIDIA Corporation
    Inventors: Mark Pereira, Ling Yang, Govendra Gupta
  • Algorithm for 64-bit address mode optimization
    Patent number: 9009686
    Abstract: One embodiment of the present invention sets forth a technique for extracting a memory address offset from a 64-bit type-conversion expression included in high-level source code of a computer program. The technique involves receiving the 64-bit type-conversion expression, where the 64-bit type-conversion expression includes one or more 32-bit expressions, determining a range for each of the one or more 32-bit expressions, calculating a total range by summing the ranges of the 32-bit expressions, determining that the total range is a subset of a range for a 32-bit unsigned integer, calculating the memory address offset based on the ranges for the one or more 32-bit expressions, and generating at least one assembly-level instruction that references the memory address offset.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: April 14, 2015
    Assignee: NVIDIA Corporation
    Inventors: Xiangyun Kong, Jian-Zhong Wang, Vinod Grover
  • System, method, and computer program product for performing graph matching
    Patent number: 9009179
    Abstract: A system, method, and computer program product are provided for performing graph aggregation. In use, a graph with a plurality of vertices and a plurality of edges is identified. Additionally, graph matching is performed on the vertices and edges of the graph by computing a graph matching, wherein the performance of the graph matching is optimized.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: April 14, 2015
    Assignee: NVIDIA Corporation
    Inventors: Jonathan Michael Cohen, Patrice Castonguay
  • METHOD AND SYSTEM FOR BUFFER LEVEL BASED FRAME RATE RECOVERY
    Publication number: 20150098020
    Abstract: Embodiments of the present invention can measure internal buffer levels (e.g., queue levels) within the sink device and dynamically adjust step size values responsive to buffer level conditions that dynamically alter the sink frame rate. As such, embodiments of the present invention can find an equivalent of the source device frame rate on the sink device based on the sink device's own clock speed. In this manner, transmission bandwidth may be preserved as clocking information does not to need to be continuously communicated between the source device and the sink device.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: Nvidia Corporation
    Inventor: Markus VILL
  • HARDWARE OVERLAY ASSIGNMENT
    Publication number: 20150100884
    Abstract: An aspect of the present invention proposes a novel approach that can reduce the total number of the overlays to be composited during the display of graphical output in a mobile computing device. As a result, the total number of memory bandwidth and the usage of a graphics processing unit by a pre-compositor can be decreased significantly. According to one embodiment, this new approach is implemented with a display panel with embedded memory which supports a partial update, or refresh feature. Which such a feature, the layer compositor (typically either the display controller or GPU) is able to keep track of actively updating regions of a display panel by checking if each layer has new content to be displayed.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: Nvidia Corporation
    Inventors: Donghan RYU, Naoya YAMOTO
  • AUDIO ENCODER PERFORMANCE FOR MIRACAST
    Publication number: 20150100324
    Abstract: A method for encoding audio comprises receiving an unencoded audio signal and monitoring a user interface for user interface events. The method continues by selecting one of a plurality of transform windows to hold a defined quantity of audio samples based upon a detected one or more user interface interaction events and associated transient information. The plurality of transform windows comprises a long window sequence comprising a single window with a first quantity of samples, and a short window sequence comprising a plurality of second windows each comprising a second quantity of samples. A sum of samples of the plurality of second windows equals the first plurality of samples. The short window sequence is selected when a particular user interface interaction event is received from the user interface.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: NVIDIA Corporation
    Inventors: Nikesh OSWAL, Vinayak WAGLE
  • SPLIT DRIVER TO CONTROL MULTIPLE GRAPHICS PROCESSORS IN A COMPUTER SYSTEM
    Publication number: 20150097844
    Abstract: A computer system includes an operating system having a kernel and configured to launch a plurality of computing processes. The system also includes a plurality of graphics processing units (GPUs), a front-end driver module, and a plurality of back-end driver modules. The GPUs are configured to execute instructions on behalf of the computing processes subject to a GPU service request. The front-end driver module is loaded into the kernel and configured to receive the GPU service request from one of the computing processes. Each back-end driver module is associated with one or more of the GPUs and configured to receive the GPU service request from the front-end driver module and pass the GPU service request to an associated GPU.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: NVIDIA Corporation
    Inventors: Kirti Wankhede, Andrew Currid, Surath Raj Mitra, Chenghuan Jia