Patents Assigned to NVidia
  • Patent number: 9053559
    Abstract: A method and system for presenting image data to a video output device is disclosed. One embodiment of the present invention sets forth a method, which includes the steps of queuing the buffer of image data for display, attaching an object to a command associated with presenting the buffer of image data, wherein the object is capable of storing timing information relating to executing the command, and enabling an application program to access the timing information.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: June 9, 2015
    Assignee: NVIDIA Corporation
    Inventors: James Jones, Jeffrey F. Juliano, Robert Morell, Thomas True, Ian M. Williams
  • Patent number: 9053209
    Abstract: A system, method, and computer program product are provided for categorizing a plurality of vertices of a graph. A predetermined plurality of random numbers is assigned to each vertex of the plurality of vertices, a determination is made whether each of the assigned predetermined plurality of random numbers of a single vertex is greater than a corresponding random number of the assigned predetermined plurality of random numbers of each of the neighbors of the single vertex, and in response to the determination, one of the assigned random numbers is selected from a group of assigned random numbers of the single vertex.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: June 9, 2015
    Assignee: NVIDIA Corporation
    Inventor: Jonathan Michael Cohen
  • Patent number: 9053041
    Abstract: A system, method, and computer program product are provided for categorizing a plurality of vertices of a graph into independent sets. A random number is assigned to each vertex in the graph and the assigned number of each vertex is compared to the assigned numbers each of the neighbors of the vertex, where all vertices in the graph that have an assigned number greater than the assigned numbers of each of their neighbors are added to a first independent set, and all vertices in the graph that have an assigned number less than the assigned numbers of each of their neighbors are added to a second independent set separate from the first independent set.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: June 9, 2015
    Assignee: NVIDIA Corporation
    Inventors: Jonathan Michael Cohen, William N. Bell, Michael J. Garland
  • Patent number: 9052897
    Abstract: Method and computing system for controlling a supply voltage in the computing system. A voltage related indication for use in setting the supply voltage of the computing system is stored, and a supply voltage is set for the computing system based on the stored voltage related indication. A crash of the computing system is detected, and in dependence thereon, an adjusted indication is determined for use in the computing system. An adjusted supply voltage is set based on the adjusted indication, and the adjusted indication is stored for further use of the computing system.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: June 9, 2015
    Assignee: Nvidia Technology UK Limited
    Inventors: Steve Felix, Pete Cumming
  • Publication number: 20150156143
    Abstract: Embodiments of the present invention are operable to display content related to an application using side display screens installed on a multi-display mobile device. As such, embodiments of the present invention can make use of the display surface areas associated with side display screens to render content (e.g., notifications associated with an application) in a power efficient manner. Also, by using separate display buffers for side display screens, embodiments of the present invention can independently render content while other components of the mobile device (e.g., the main display screen) operate within low power mode or “sleep state.” As such, by using side display screen in this fashion, embodiments of the present invention can efficiently utilize the power and computational resources of the mobile device.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 4, 2015
    Applicant: Nvidia Corporation
    Inventors: Harshal CHOPDE, Manish TIWARI, Ankit MENDIRATTA, Abhishek KUMAR
  • Publication number: 20150153805
    Abstract: A clocked electronic device includes first and second control systems. The first control system is configured to decrease clock frequency in the device in response to decreasing supply voltage. The second control system is responsive to clock lag in the device and to an amount of current drawn through the device. It is configured to increase the supply voltage in response to increasing clock lag, but to decrease the supply voltage when the current drawn through the device exceeds an operational threshold.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 4, 2015
    Applicant: NVIDIA Corporation
    Inventor: Shuang Xu
  • Publication number: 20150154934
    Abstract: Embodiments of the present invention provide a novel solution that uses subjective end-user input to generate optimal image quality settings for an application. Embodiments of the present invention enable end-users to rank and/or select various adjustable application parameter settings in a manner that allows them to specify which application parameters and/or settings are most desirable to them for a given application. Based on the feedback received from end-users, embodiments of the present invention may generate optimal settings for whatever performance level the end-user desires. Furthermore, embodiments of the present invention may generate optimal settings that may be benchmarked either on a server farm or on an end-user's client device.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 4, 2015
    Applicant: Nvidia Corporation
    Inventors: John SPITZER, Rev LEBAREDIAN, Tony TAMASI
  • Publication number: 20150153544
    Abstract: Embodiments of the present invention utilize an attachable lens board that can be secured to the back of a mobile device and placed in a position that is proximate to the built-in camera lens associated with the camera system of the mobile device. As such, the lens board can be positioned to accurately align several different auxiliary camera lenses, each installed within various camera lens receivers formed within the lens board, with the built-in camera lens for focusing and/or image capture. Additionally, embodiments of present invention can include circuitry within the lens board that can be used to identify the types of lenses currently installed within each camera lens receiver. In this manner, embodiments of the present invention can correct possible optical imperfections of resultant images produced by the combination of the built-in camera lens and auxiliary lens selected for focusing and/or image capture by the user.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 4, 2015
    Applicant: Nvidia Corporation
    Inventor: Christen PEDERSEN
  • Publication number: 20150154733
    Abstract: A raster operations (ROP) unit is configured to compress stencil values included in a stencil buffer. The ROP unit divides the stencil values into groups, subdivides each group into two halves, and selects an anchor value for each half. If the difference between each of the stencil values and the corresponding anchor lies within an offset range, and the difference between the two anchors lies within a delta range, then the group is compressible. For a compressible group, the ROP unit encodes the anchor value, offsets from anchors, and an anchor delta. This encoding enables the ROP unit to operate on the compressed group instead of the uncompressed stencil values, reducing the number of memory and computational operations associated with the stencil values. Consequently, the ROP unit reduces memory bandwidth use, reduces power consumption, and increases rendering rate compared to conventional ROP units that implement less flexible compression techniques.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Christian AMSINCK, Bengt-olaf SCHNEIDER, Jeffrey A. BOLZ
  • Publication number: 20150156483
    Abstract: A method includes interleaving, through a processor of a data processing device communicatively coupled to a memory and/or a processor of a data source communicatively coupled to the data processing device, each of a data and another data within a data frame. The each of the data and the another data corresponds to a distinct set of video data, image data and/or audio data. The method also includes rendering, through the processor of the data processing device, the data frame on a display unit and/or one or more audio endpoint device(s) associated with the data processing device following the interleaving therewithin, and providing a capability to view and/or listen to solely the data or the another data from the rendered data frame on the display unit and/or the one or more audio endpoint device(s).
    Type: Application
    Filed: December 3, 2013
    Publication date: June 4, 2015
    Applicant: NVIDIA Corporation
    Inventors: Anup Rathi, Nahush Bhanage
  • Publication number: 20150153777
    Abstract: Systems and methods for providing a user interface by using a flexible display screen as well as an inflexible display screen. The dual display screens are installed on the same electronic device and may be used to display information simultaneously or alternatively. The flexible display screen can display information in an expanded position and is substantially compacted in size in a retracted position. In response to a user request, the flexible display screen can automatically wind around a rotatable axial connector. The inflexible touchscreen may serve to receive user input with respect to the content displayed on the flexible display screen. An instant size of the flexible display screen can be detected by a sensor and used to adapt a format of the content displayed on the flexible display screen.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 4, 2015
    Applicant: NVIDIA Corporation
    Inventors: Laurence LIU, Richard LAI
  • Publication number: 20150154732
    Abstract: One embodiment of the present invention sets forth a method for compositing surface buffered data for display. The method includes identifying a first set of memory mappings that associates a first set of contiguous virtual addresses with a first set of image data. The method also includes identifying a second set of memory mappings that associates a second set of contiguous virtual addresses with a second set of image data. The method further includes generating a third set of memory mappings based on the first set of memory mappings and the second set of memory mappings that associates a third set of contiguous virtual addresses with both the first set of image data and the second set of image data. Further embodiments provide, among other things, a computing device, a display subsystem, and a non-transitory computer-readable medium configured to carry out method steps set forth above.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 4, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Kirill ARTAMONOV, Michael FRYDRYCH
  • Patent number: 9047085
    Abstract: A method and apparatus for controlling sparse refresh of a self-refreshing display device coupled to a graphics controller are disclosed. The display device includes capabilities to drive the display based on video signals generated from a local frame buffer. The graphics controller may optimally be placed in one or more power-saving states when the display device is operating in a panel self-refresh mode. When exiting the power-saving state to update the image displayed by the display device, a fast-resume initialization routine may be run to reconfigure the GPU when operating in a sparse refresh mode, i.e., where the image being displayed on the display device is updated infrequently. In such cases, the graphics controller may be configured to receive instructions and data from a central processing unit via an alternative low-bandwidth communications path instead of the high-bandwidth communications path used in normal operation.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: June 2, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: David Wyatt, David Matthew Stears
  • Publication number: 20150146993
    Abstract: A method for encoding at least one extra bit in an image compression and decompression system. The method includes accessing an input image, and compressing the input image into a compressed image using an encoder system, wherein said encoding system implements an algorithm for encoding at least one extra bit. The method further includes communicatively transferring the compressed image to a decoding system, and decompressing the compressed image into a resulting uncompressed image that is unaltered from said input image, wherein the algorithm for encoding enables the recovery of the at least one extra bit.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Walter E. DONOVAN, Marilyn J. LANG
  • Publication number: 20150149788
    Abstract: A system, method, and computer program product are provided for implementing asymmetric AES-CBC (Advanced Encryption Standard-Cipher Block Chaining) channels usage between encryption and decryption of data. In operation, data to be written to memory is identified. In addition, the data is encrypted utilizing a first AES-CBC channel. Additionally, at least one of a plurality of AES-CBC channels is utilized to decrypt the data to achieve a determined performance target.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: NVIDIA Corporation
    Inventors: Karan Gupta, Brahmanandam Karuturi, Jay S. Huang
  • Publication number: 20150149713
    Abstract: An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: Nvidia Corporation
    Inventors: Michael Asbury Woodmansee, J. Arjun Prabhu
  • Publication number: 20150145871
    Abstract: A method, system, and computer-program product are provided to enable the yielding by threads executing in a processing unit to transfer control to a host processor. The method includes the steps of receiving an intermediate representation of a program, replacing a yield instruction in the intermediate representation with a yield operation that includes one or more instructions, and compiling at least a portion of the modified intermediate representation into a machine code for execution on a parallel processing unit.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: NVIDIA Corporation
    Inventors: Steven Parker, Andreas Dietrich
  • Patent number: 9041719
    Abstract: A method for transparently directing data in a multi-GPU system. A driver application receives a first plurality of graphics commands from a first graphics application and selects a first GPU from the multi-GPU system to exclusively process the first plurality of graphics commands. The first plurality of graphics commands is transmitted to the first GPU for processing and producing a first plurality of renderable data. The first plurality of renderable data is stored in a first frame buffer associated with the first GPU. A second plurality of graphics commands is received from a second graphics application and a second GPU is selected to exclusively process the second plurality of graphics commands. The second GPU processing the second plurality of graphics commands produces a second plurality of renderable data. The second plurality of renderable data is stored in a second frame buffer associated with the second GPU.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: May 26, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Andreas Wolf
  • Patent number: 9041721
    Abstract: A system, method, and computer program product are provided for evaluating an integral utilizing a low discrepancy sequence and a block size. In use, a low discrepancy sequence and a block size are determined. Additionally, an integral is evaluated, utilizing the low discrepancy sequence and the block size.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 26, 2015
    Assignee: NVIDIA Corporation
    Inventors: Alexander Keller, Nikolaus Binder
  • Publication number: 20150143061
    Abstract: A system includes a processing unit and a register file. The register file includes at least a first memory structure and a second memory structure. The first memory structure has a lower access energy than the second memory structure. The processing unit is configured to address the register file using a single logical namespace for both the first memory structure and the second memory structure.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Nvidia Corporation
    Inventors: Brucek Kurdo Khailany, Mark Alan Gebhart