Abstract: Voice trigger. In accordance with a first method embodiment, a long term average audio energy is determined based on a one-bit pulse-density modulation bit stream. A short term average audio energy is determined based on the one-bit pulse-density modulation bit stream. The long term average audio energy is compared to the short term average audio energy. Responsive to the comparing, a voice trigger signal is generated if the short term average audio energy is greater than the long term average audio energy. Determining the long term average audio energy may be performed independent of any decimation of the bit stream.

Abstract: A system, method, and computer program product are provided for performing fast, non-rigid registration for at least two images of a high-dynamic range image stack. The method includes the steps of generating a warped image based on a set of corresponding pixels, analyzing the warped image to detect unreliable pixels in the warped image, and generating a corrected pixel value for each unreliable pixel in the warped image. The set of corresponding pixels includes a plurality of pixels in a source image, each pixel in the plurality of pixels associated with a potential feature in the source image and paired with a corresponding pixel in a reference image that substantially matches the pixel in the source image.

Abstract: A method for loading a shader program from system memory into GPU memory. The method includes accessing the shader program in system memory of a computer system. A DMA transfer of the shader program from system memory into GPU memory is performed such that the shader program is loaded into GPU memory in an address independent manner.

Abstract: A method for efficiently managing memory resources in a computer system having a graphics processing unit that runs several processes simultaneously on the same computer system includes using threads to communicate that additional memory is needed. If the request indicates that termination will occur then the other processes will reduce their memory usage to a minimum to avoid termination but if the request indicates that the process will not run optimally then the other processes will reduce their memory usage to 1/N where N is the count of the total number of running processes. The apparatus includes a computer system using a graphics processing unit and processes with threads that can communicate directly with other threads and with a shared memory which is part of the operating system memory.

Abstract: One embodiment of the present invention sets forth a technique for performing a computer-implemented method for tessellating patches. An input block is received that defines a plurality of input patch attributes for each patch as well as instructions for processing each input patch. A plurality of threads is launched to execute the instructions to generate each vertex of a corresponding output patch based on the input patch. Reads of values written during instruction execution are synchronized so threads can read and further process the values of other threads. An output patch is then assembled from the outputs of each of the threads; and emitting the output patch for further processing.

Abstract: A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency Fc. The method comprises selecting the clock frequency Fc to be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fc is selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal.

Abstract: Embodiments of the present invention provide a novel solution which can be used to detect and analyze instances of micro stutter within a given game, GPU and/or driver version. Embodiments of the present invention may be operable to divide an application session into a set of sub-sessions and perform multiple derivative calculations on time-varying application parameters (e.g., frame rates) measured during each sub-session. Embodiments of the present invention may also be operable to generate separate histograms for each derivative calculation performed. As such, based on calculations performed, embodiments of the present invention may synchronously increment histogram bins representing a corresponding range of performance in real-time. Upon the completion of the application session, sub-session histograms may be compressed and then saved into a log which can be fetched and uploaded to a host computer system for aggregation and storage into a database for server-side optimization analysis.

Abstract: A method includes distinctly assigning, through a driver component, each audio channel of multichannel audio data in a memory of a data processing device to one or more audio endpoint device(s) of a number of audio endpoint devices communicatively coupled to the data processing device. Each audio endpoint device of the number of audio endpoint devices is capable of supporting a number of audio channels less than a number of audio channels of the multichannel audio data. The method also includes routing, through a processor of the data processing device communicatively coupled to the memory, audio data related to the each audio channel to the appropriate one or more audio endpoint device(s) based on the assignment through the driver component to enable rendering of the multichannel audio data on the number of audio endpoint devices.

Abstract: A subsystem is configured to apply a voltage source to a gated circuit domain in a manner that limits in-rush current and affords minimal time delay. A control signal turns on a wake-up switch that connects the voltage source to the domain. The equivalent series resistance of the wake-up switch has a magnitude that limits the transient charge current to the gated domain. A digital control circuit monitors the resulting rising domain voltage and determines when the domain voltage reaches operating level, at which point additional transient current will be minimal. The control circuit then activates a primary switch that connects the voltage source to the domain through a series resistance of negligible magnitude. An adjustment element provides the option to permanently set a control signal that marginally reduces the time at which the control circuit activates the primary switch to compensate for variations in circuit parameters.

Abstract: AVC decoding techniques include parsing a set of alternating slices of one or more picture frames and parsing another set of alternating slices of the one or more picture frames. The parsed set of alternating slices of the one or more picture frames are buffered separately from the parsed other set of alternating slices of the one or more picture frames. The buffered parsed set of alternating slices and the other buffered parsed set of alternating slices are alternating decoded.

Abstract: A method includes scanning, through a processor of a data processing device communicatively coupled to a memory, display data to be rendered on a display unit communicatively coupled to the data processing device for boundaries of one or more virtual object(s) therein. The method also includes rendering, through the processor, a portion of the display data outside the boundaries of the one or more virtual object(s) at a reduced level compared to a portion of the display data within the boundaries on the display unit.

Abstract: An image signal processor (ISP) and a method of generating image statistics. One embodiment of the ISP includes: (1) a client configured to employ image statistics to process a current frame of a scene if changes in the current frame relative to a previous frame of the scene rise above a threshold, and (2) a statistics engine associated with the client and configured to generate the image statistics based on the current frame if the changes rise above the threshold.

Abstract: The description is directed to systems and methods for restoring a program state retained from a prior execution session on a virtual machine. On receiving a request to execute a program an image of user-independent files are mounted to a virtual machine. Specified user-modifiable files are copied from a particular user storage location to put the program in a condition to execute the program so that it begins from the previously-existing program state. During the session at least some of the files are modified and on a session end the user-modifiable files are saved to the particular user storage location to retain the updated program state.

Abstract: An input output connector for a graphics processing unit having a graphics pipeline including fixed function units and programmable function units is disclosed. Additionally, a graphics processing unit and a method of operating a graphics pipeline are disclosed. In one embodiment, the input output connector includes: (1) a request arbiter configured to connect to each of the programmable function units, receive fixed function requests therefrom and arbitrate the requests and (2) fixed unit converters, wherein each of the fixed unit converters is dedicated to a single one of the fixed function units and is configured to convert the requests directed to the single one to an input format for the single one.

Abstract: A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based intermediate representation of a hardware design stored in a source database. An instance of each unique module in the source database is determined and a hardware module node is generated for each unique module. Additionally, a list of one or more instances is associated with each hardware module node and a graph-based common representation of the hardware design that includes one or more of the generated hardware module nodes is stored.

Abstract: A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction.

Abstract: A system, method, and computer program product are provided for mapping tiles to physical memory locations. In use, a plurality of virtual tiles associated with a texture is identified. Additionally, a request to perform a mapping of the plurality of virtual tiles to one or more physical memory locations is received. Further, the plurality of virtual tiles is mapped to the one or more physical memory locations, utilizing a page table.

Abstract: A video capture utility and method for a computer system. In one embodiment, the video capture utility includes: (1) a circular buffer allocated in a memory of the computer system to store at most a predefined video length, (2) a video output interceptor executable in a processor of the computer system and operable to receive and store video output most recently generated by an application program and (3) a video output extractor executable in the processor and operable to prompt contents of the circular buffer to be copied from the circular buffer to another location.

Abstract: A system for, and method of, computing reduced-resolution indirect illumination using interpolated directional incoming radiance and a graphics processing subsystem incorporating the system or the method. In one embodiment, the system includes: (1) a cone tracing shader executable in a graphics processing unit to compute directional incoming radiance cones for sparse pixels and project the directional incoming radiance cones on a basis and (2) an interpolation shader executable in the graphics processing unit to compute outgoing radiance values for untraced pixels based on directional incoming radiance values for neighboring ones of the sparse pixels.

Abstract: A graphics processing subsystem and method for computing a 3D clipmap. One embodiment of the subsystem includes: (1) a renderer operable to render a primitive surface representable by a 3D clipmap, (2) a geometry shader (GS) configured to select respective major-plane viewports for a plurality of clipmap levels, the major-plane viewports being sized to represent full spatial extents of the 3D clipmap relative to a render target (RT) for the plurality of clipmap levels, (3) a rasterizer configured to employ the respective major-plane viewports and the RT to rasterize a projection of the primitive surface onto a major plane corresponding to the respective major-plane viewports into pixels representing fragments of the primitive surface for each of the plurality of clipmap levels, and (4) a plurality of pixel shader (PS) instances configured to transform the fragments into respective voxels in the plurality of clipmap levels, thereby voxelizing the primitive surface.