Abstract: An aspect of the present invention proposes a novel approach that can reduce the total number of the overlays to be composited during the display of graphical output in a mobile computing device. As a result, the total number of memory bandwidth and the usage of a graphics processing unit by a pre-compositor can be decreased significantly. According to one embodiment, this new approach is implemented with a display panel with embedded memory which supports a partial update, or refresh feature. Which such a feature, the layer compositor (typically either the display controller or GPU) is able to keep track of actively updating regions of a display panel by checking if each layer has new content to be displayed.

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

Abstract: A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map.

Abstract: One embodiment of the present invention includes techniques to decrease power consumption by reducing the number of redundant operations performed. In operation, a streamlining multiprocessor (SM) identifies uniform groups of threads that, when executed, apply the same deterministic operation to uniform sets of input operands. Within each uniform group of threads, the SM designates one thread as the anchor thread. The SM disables execution units assigned to all of the threads except the anchor thread. The anchor execution unit, assigned to the anchor thread, executes the operation on the uniform set of input operands. Subsequently, the SM sets the outputs of the non-anchor threads included in the uniform group of threads to equal the value of the anchor execution unit output. Advantageously, by exploiting the uniformity of data to reduce the number of execution units that execute, the SM dramatically reduces the power consumption compared to conventional SMs.

Abstract: The disclosure is directed to a system and method for selectively controlling display power consumption in a system with a first and second display. While the system is in a non-idle state and while an application that is actively executing has an active window on the first display, a determination is made that the second display is inactive. In response to the determination, and while the system is still in the non-idle state, the second display is switched from a full power state to a low power state.

Abstract: Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row.

Abstract: A technique for stereographic display of a selection marquee in a scene includes receiving the selection marquee in a two-dimensional viewpoint at a near plane of the scene. A selection volume is generated from which the fragments of a scene associated with the selection marquee are determined. A two-dimensional stereoscopic representation of the three-dimensional scene, including the selection marquee at the associated fragments, may then be rendered.

Abstract: The muxed HDMI debug port methods and apparatuses are directed toward means for detecting an extended display identification data (EDID) code indicating a debug cable or debug host device coupled to the high-definition multimedia interface (HDMI) port of a computing device. In addition, the methods and apparatuses include means for disabling a display data channel (DDC) bus of the high-definition multimedia interface (HDMI) port in response to the extended display identification data (EDID) code indicating the debug cable or debug host device. Furthermore, the method and apparatuses include means for transmitting and receiving debug commands and data on a serial input (RXD) and serial output (TXD) of the high-definition multimedia interface (HDMI) port in response to the extended display identification data (EDID) code indicating the debug cable or debug host device.

Abstract: One embodiment of the present invention sets forth a technique for automatically provisioning a diskless computing device and an associated server system. A diskless computing device client incorporates an iSCSI initiator that is used to access resources provided by an iSCSI target that is resident on a server computing device. The iSCSI initiator is implemented in the client firmware, providing INT13 disk services entry points, thereby enabling the client to transparently access virtual storage devices at boot time. The client device conducts an apparently local installation using the virtual storage devices provided by the server computing device. A short signature value is associated with the boot image, uniquely associating the boot image with the specific client hardware configuration. When the client device boots normally, the signature value of the client device is presented to the server computing device to automatically reference the appropriate boot image.

Abstract: Method, apparatuses, and systems are presented for processing a sequence of images for display using a display device involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the sequence of images, including a second image, delaying processing of the second image by the at least one second graphics device, by a specified duration, relative to processing of the first image by the at least one first graphics device, to stagger pixel data output for the first image and pixel data output for the second image, and selectively providing output from the at least one first graphics device and the at least one second graphics device to the display device.

Abstract: A method and system for restoring output to a display device. The method includes receiving a request to restore the output, modifying output timing so output is visible on a display device, and invoking an output configuration application. The method and system allow a user to restore the output on a display device after the output has been configured to settings which exceed the capabilities of the display device.

Abstract: A method for compressing graphics data comprises selecting z-planes from a plurality of z-planes. The selected z-planes are predictor z-planes. A residual is determined for each sample not covered by one of the predictor z-planes. A sample is covered by one of the predictor z-planes when the predictor z-plane correctly defines a z-value of the sample. A residual comprises a value that is a difference between a predicted z-value provided by one of the predictor z-planes and an actual z-value for the sample. The predictor z-planes and the residuals are stored in a z-buffer.

Abstract: A method to render graphics on a computer system having a plurality of graphics-processing units (GPUs) includes the acts of instantiating an independent physical-memory allocator for each GPU, receiving a physical-memory allocation request from a graphics-driver process, and passing the request to one of the independent physical-memory allocators. The method also includes creating a local physical-memory descriptor to reference physical memory on the GPU associated with that physical-memory allocator, assigning a physical-memory handle to the local physical-memory descriptor, and returning the physical-memory handle to the graphics-driver process to fulfill a subsequent memory-map request from the graphics-driver process.

Abstract: One embodiment of the present invention includes a method for simplifying arithmetic operations by detecting operands with elementary values such as zero or 1.0. Computer and graphics processing systems perform a great number of multiply-add operations. In a significant portion of these operations, the values of one or more of the operands are zero or 1.0. By detecting the occurrence of these elementary values, math operations can be greatly simplified, for example by eliminating multiply operations when one multiplicand is zero or 1.0 or eliminating add operations when one addend is zero. The simplified math operations resulting from detecting elementary valued operands provide significant savings in overhead power, dynamic processing power, and cycle time.

Abstract: A simulation engine performs a mass-conserving Eulerian fluid simulation by manipulating the distribution of density between nodes associated with the fluid simulation. The simulation engine traces a velocity field upstream to identify the source of mass that currently resides at a given node. The simulation engine then adjusts (i) the density contributions to that source from adjacent nodes and (ii) the density contributions provided by that source to the given node. In doing so, the simulation engine maintains conservation of mass at a local level between nodes within a given neighborhood. As a result, mass is conserved at a global level. One advantage of the disclosed technique is that a fluid interface associated with the fluid simulation may appear physically realistic, because numerical errors typically caused by violations of conservation of mass may be eliminated.

Abstract: A method includes executing an instance of a process on each of a data processing device and one or more another data processing device(s), and authenticating, registering or pairing the one or more another data processing device(s) with the data processing device through a Personal Area Network (PAN) associated with a user of the data processing device and/or a computer network based on an identifier. The method also includes sharing content generated and/or stored in the data processing device with the one or more another data processing device(s) through the PAN and/or the computer network, and providing, through the execution of the instance of the process, a capability to the user of the data processing device to control the sharing of the content with the one or more another data processing device(s). The control of the sharing includes restricting the sharing based on controlling a parameter of the sharing.

Abstract: A physics simulation engine simulates the motion of one or more particles that represent virtual objects in a virtual graphics scene. Each particle is assigned to a level in a particle hierarchy that has at least two levels. The physics simulation engine collapses constraints associated with particles assigned to a first level of the particle hierarchy to generate hierarchical constraints associated with particles assigned to the second level of the particle hierarchy. The physics simulation engine updates the position of each particle assigned to the second level of the particle hierarchy by enforcing constraints associated with the particle. The physics simulation engine then updates the position of each particle assigned to the first level of the particle hierarchy based on the positions of the particles assigned to the second level of the particle hierarchy.

Abstract: A system, method, and computer program product are provided for efficiently performing a scan operation. In use, an array of elements is traversed by utilizing a parallel processor architecture. Such parallel processor architecture includes a plurality of processors each capable of physically executing a predetermined number of threads in parallel. For efficiency purposes, the predetermined number of threads of at least one of the processors may be executed to perform a scan operation involving a number of the elements that is a function (e.g. multiple, etc.) of the predetermined number of threads.

Abstract: An Optimized Personal Computer (OPC) system may be a multi-functional processing unit with ultra-low power consumption and may consist of a single chip having a plurality of processors thereon. Each processor may be specialized for tasks including computing, graphic processing and audio processing. The OPC may be connected to a mother board, a memory unit and an I/O interface. The OPC may be connected to a primary PC (either in an expansion slot or in a drive bay) via a USB connection, for example, and be configured to run continuously and take over certain tasks from the primary PC as needed while the primary PC hibernates. The OPC may also be embedded in a monitor or other peripheral devices.

Abstract: One embodiment sets forth a technique for N-way memory barrier operation coalescing. When a first memory barrier is received for a first thread group execution of subsequent memory operations for the first thread group are suspended until the first memory barrier is executed. Subsequent memory barriers for different thread groups may be coalesced with the first memory barrier to produce a coalesced memory barrier that represents memory barrier operations for multiple thread groups. When the coalesced memory barrier is being processed, execution of subsequent memory operations for the different thread groups is also suspended. However, memory operations for other thread groups that are not affected by the coalesced memory barrier may be executed.