Abstract: A method includes monitoring, through a battery driver component of a embedded operating system executing on a data processing system deriving power from a battery, a state of the battery. The method also includes modifying, through a backlight driver component of the embedded operating system, an intensity level of a backlight of one or more Input/Output (I/O) devices of the data processing system from a current level associated with a normal operation thereof to an intensity level lower than the current level when the battery is detected to be in a critical state to prolong a lifetime thereof. The critical state is associated with a remaining charge on the battery being below a threshold required to maintain the data processing system in a powered on state.

Abstract: One embodiment sets forth a technique for N-way memory barrier operation coalescing. When a first memory barrier is received for a first thread group execution of subsequent memory operations for the first thread group are suspended until the first memory barrier is executed. Subsequent memory barriers for different thread groups may be coalesced with the first memory barrier to produce a coalesced memory barrier that represents memory barrier operations for multiple thread groups. When the coalesced memory barrier is being processed, execution of subsequent memory operations for the different thread groups is also suspended. However, memory operations for other thread groups that are not affected by the coalesced memory barrier may be executed.

Abstract: Hardware resource sharing for a computerized system running software tasks. A mutex controller is associated with the hardware resource. Lock and unlock indicators are settable by a software task and readable by the controller, and locked and waiters flags are settable and readable by the controller. The controller monitors whether the lock indicator has been set and determines whether the locked flag is set. If not, it sets the locked flag and, if so, it sets the waiters flag and asserts a mutex interrupt signaling the computer system to divert the software task to run a lock request routine. The controller also monitors whether the unlock indicator has been set and then determines whether the waiters flag is set. If not, it clears the locked flag and, if so, it asserts a mutex interrupt signaling the computer system to divert the software task to run an unlock request routine.

Abstract: One embodiment provides a method to store electrical energy in an electronic device, which has a central processing unit (CPU) to provide operating-system and application processing in the device. The method includes controlling, from the CPU of the electronic device, communication sent from the device and received at a wireless charger within communication range of the device. The method further includes computing, in the CPU of the electronic device, a set-point condition for wireless energy flow from the wireless charger to an energy-storage component of the device, and regulating the wireless energy flow based on the set-point condition.

Abstract: A system, method, and computer program product are provided for implementing a multi-cycle register file bypass mechanism. The method includes the steps of receiving a set of control bits, combining the set of control bits with a set of valid bits associated with previously issued instructions, and enabling a bypass path for each thread based on the set of control bits and the set of valid bits. Each valid bit in the set of valid bits indicates whether execution of an instruction of the previously issued instructions was enabled for a thread in a thread block.

Abstract: A system, method, and computer program product are provided for processing a screen-aligned rectangle within a processing pipeline. The method includes the steps of determining coordinates for a screen-aligned rectangle by projecting a specification line onto a screen-space plane, computing a plane equation associated with the specification line, and rasterizing the screen-aligned rectangle that is within the screen-space plane based on the coordinates and the plane equation. The specification line is within a three-dimensional (3D) space. The plane equation is associated with a rendering parameter for the screen-aligned rectangle. The plane equation may be evaluated by a pixel shader in conjunction with processing the screen-aligned rectangle.

Abstract: Using face detection procedures, embodiments of the present invention can detect the presence of multiple of contacts within an image. Embodiments of the present invention can also associate the faces detected within the image with contacts belonging to a list of contacts stored on a mobile device. Additionally, embodiments of the present invention are operable to store contact information associated with recognizable contacts found into the image. In this fashion, upon rendering an image, the user can automatically call a contact in the image by clicking on the contact's image or can automatically create a conference call by clicking on more than one contact present in the image. Furthermore, embodiments of the present invention allow users to provide contact information manually during storage procedures for any unrecognized subjects found in the image. Furthermore, embodiments of the present invention can encrypt contact information stored within the image.

Abstract: Computer and graphics processing elements, connected generally in series, form a pipeline. Circuit elements known as di/dt throttles are inserted within the pipeline at strategic locations where the potential exists for data flow to transition from an idle state to a maximum data processing rate. The di/dt throttles gently ramp the rate of data flow from idle to a typical level. Disproportionate current draw and the consequent voltage droop are thus avoided, allowing an increased frequency of operation to be realized.

Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.

Abstract: Various embodiments relating to image capture with a camera and generation of a processed image having desired image characteristics are provided. In one embodiment, a plurality of images of a scene captured by a camera and associated image metadata are stored. Image metadata associated with each image of the plurality of images includes image characteristics of that image, and each image has a different set of values of image characteristics. A request for an image of the scene that most closely matches a specified image characteristic profile that defines one or more values of one or more image characteristics is received. The image characteristic profile is compared to image metadata of each of the plurality of images. A processed image generated from the plurality of images of the scene having image characteristics that most closely match the image characteristic profile based on the comparison is provided.

Abstract: An issue control unit is configured to control the rate at which an instruction issue unit issues instructions to an execution pipeline in order to avoid spikes in power drawn by that execution pipeline. The issue control unit maintains a history buffer that reflects, for N previous cycles, the number of instructions issued during each of those N cycles. If the total number of instructions issued during the N previous cycles exceeds a threshold value, then the issue control unit throttles the instruction issue unit from issuing instructions during a subsequent cycle. In addition, the issue control unit increases the threshold value in proportion to the number of previously issued instructions and based on a variety of configurable parameters. Accordingly, the issue control unit maintains granular control over the rate with which the instruction issue unit “ramps up” to a maximum instruction issue rate.

Abstract: A debug controller monitors a tip-ring-ring-shield (TRRS) socket, within a form factor device, to detect whether a debug unit is transmitting a request for a TRRS socket debug connection. The form factor device also includes a system on chip (SoC), a switch, and an audio codec. The SoC includes the debug controller and a software debug interface. The switch couples a right audio lead and left audio lead of the TRRS socket to the audio codec. If the debug controller detects the request from the debug unit, then the debug controller instructs the switch to establish a TRRS socket debug connection. The switch establishes the TRRS socket debug connection by coupling right audio lead and left audio lead to the software debug interface instead of the audio codec. This establishment of the TRRS socket debug connection eliminates the need for manual configuration of the TRRS socket debug connection.

Abstract: A parallel counter accesses data generated by an application and stored within a register. The register includes different segments that include different portions of the application data. The parallel counter is configured to count the number of values within each segment that have a particular characteristic in a parallel fashion. The parallel counter may then return the individual segment counts to the application, or combine those segment counts and return a register count to the application. Advantageously, applications that rely on population count operations may be accelerated. Further, increasing the number of segments in a given register may reduce the time needed to count the values in that register, thereby providing a scalable solution to population counting. Additionally, the architecture of the parallel counter is sufficiently flexible to allow both register counting and segment counting, thereby combining two separate functionalities into just one hardware unit.

Abstract: Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.

Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.

Abstract: A security command protocol provides secure authenticated access to an auxiliary security memory within a SCSI storage device. The auxiliary security memory acts as an authenticated separate secure storage area that stores sensitive data separately from the user data area of the SCSI storage device. The security command protocol is used to access the auxiliary security memory. The security command protocol allows a trusted execution environment to transport sensitive data to and from storage in the auxiliary security memory. The regular execution environment does not have access to the security command protocol or the auxiliary security memory. The security command protocol and auxiliary security memory eliminate the need for additional secure storage components in devices that provide the security features of firmware TPM.

Abstract: Various embodiments relating to image capture with a camera and generation of a processed image having desired image characteristics are provided. In one embodiment, a suggested range of values of one or more image characteristics based on preferences of one or more sources is received. Furthermore, settings of the camera are adjusted to capture a plurality of images of a scene. Each image has a different set of values within the suggested range of values of the one or more image characteristics.

Abstract: A software or hardware agent running on a personal computing (PC) device provides allows a consumer electronic device connected to the PC device over a high definition multimedia interface (HDMI) network to control the PC device using standardized commands. This enables a user to control the PC device and other consumer electronic devices that are connected to the HDMI network using a single interface. The agent responds as a consumer electronic device and translates the standardized commands as universal serial bus (USB) human interface device (HID) input reports to the PC device operating system. The agent represents the specific capabilities of the PC device as standard consumer electronic device controls.

Abstract: A static random-access memory (SRAM) module includes a column select (RSEL) driver coupled to an input/output (I/O) circuit by an RSEL line. The I/O circuit is configured to read bit line signals from a bit cell within the SRAM module. During a read operation, the RSEL driver pulls the RSEL line to zero in order to cause p-type metal-oxide-semiconductors (PMOSs) within the I/O circuit to sample the bit line signals output by the bit cell. In response, an aggressor driver drives the RSEL line to a negative voltage, thereby reducing the resistance of the PMOSs within the I/O circuit.

Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.