Abstract: A method of calculating performance parameters for a type of data being executed by a unified processing subunit. In one embodiment, a task (e.g., a draw call) is executed by a processing pipeline (e.g., a GPU). An ALU within a unified processing subunit (e.g., a unified shader processing unit) is queried to determine a type of data (e.g., vertex processing, pixel shading) being processed by the ALU. Performance parameters (e.g., bottleneck and utilization) for the type of data being processed by the ALU is calculated and displayed (e.g., stacked graph). Accordingly, software developers can visualize component workloads of a unified processing subunit architecture. As a result, utilization of the unified processing subunit processing a particular data may be maximized while bottleneck is reduced. Therefore, the efficiency of the unified processing subunit and the processing pipeline is improved.

Abstract: Techniques for the discovery of a topology of varying complexity and discovery of the capability of the devices of the topology include querying a plurality of node devices for node data. At least an initial portion of node data of one or more node devices is received in response to the query. In addition, previously determined node data is retrieved from a cache. The initial portion of node data is correlated to the previously determined node data to deduce node data for one or more node devices within a predetermined period of time. It is to be appreciated that the deduced node data may include node data beyond the initial portion of node data and/or node data for other node devices beyond the initially responding node devices. The deduced node data may then be reported to an operating system.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for author verification and authorization of object code. In one embodiment, program object code is linked with a plurality of data blocks to create linked object code and a MAP file. Thereafter, author verification is performed by executing a plurality of comparisons between the linked object code and the MAP file. In another embodiment, a digital signing procedure is performed on linked object code by creating a signature data block. The signature data block is then encrypted and written to the linked object code to create digitally-signed object code. In another embodiment, an application program embodied in linked object code generates a data packet. The data packet is then compared to a previously-generated signature data packet from the linked object code to determine if the linked object code is authorized.

Abstract: One embodiment of the present invention sets forth a method for accessing display configuration information of a display device in a multi-graphics-processing-unit (multi-GPU) system based on a hot-plug detection signal associated with the same display device. The method includes the steps of changing the power state of a discrete GPU (dGPU) in the multi-GPU coupled to the display device after having detected an assertion of the hot-plug detection signal, retrieving the display configuration information of the display device with the dGPU, and powering down the dGPU after having retrieved the display configuration information.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained.

Abstract: A modem is disclosed. An embodiment thereof includes: a first interface arranged to connect to a network, a second interface arranged to connect to a host processor on the terminal, an audio interface arranged to connect to an audio processing means and a processing unit arranged to receive a plurality of parameters from the terminal via the second interface. The plurality of parameters are associated with a call established by the host processor to at least one further terminal connected to the network; wherein the processing unit is further arranged to receive input voice data from the audio processing means, process the input voice data in dependence on at least one of said parameters; and transmit the processed input voice data via the first interface to the at least one further terminal over said network during the call in dependence on a further at least one of said parameters.

Abstract: One embodiment of the invention sets forth a method for transmitting display data to a display device. The method includes the steps of receiving a contract for a frame of display data, preparing the frame of display data to ensure the timing requirements of the display device can be satisfied based on the contract, and transmitting the frame of display data to the display device while the contract is pending.

Abstract: A method for displaying a near-eye light field display (NELD) image is disclosed. The method comprises determining a pre-filtered image to be displayed, wherein the pre-filtered image corresponds to a target image. It further comprises displaying the pre-filtered image on a display. Subsequently, it comprises producing a near-eye light field after the pre-filtered image travels through a microlens array adjacent to the display, wherein the near-eye light field is operable to simulate a light field corresponding to the target image. Finally, it comprises altering the near-eye light field using at least one converging lens, wherein the altering allows a user to focus on the target image at an increased depth of field at an increased distance from an eye of the user and wherein the altering increases spatial resolution of said target image.

Abstract: A technique for encoding digital video data comprises determining an estimated number of real bits associated with performing one or more entropy encoding operations on a coding unit of digital video data. Based on the estimated number of real bits, an estimated cost of compressing the coding unit using a compression technique is determined, and the compression technique is selected to compress the coding unit based at least in part on the estimated cost.

Abstract: One embodiment sets forth a method for transforming 3-D images into 2-D rendered images using render target sample masks. A software application creates multiple render targets associated with a surface. For each render target, the software application also creates an associated render target sample mask configured to select one or more samples included in each pixel. Within the graphics pipeline, a pixel shader processes each pixel individually and outputs multiple render target-specific color values. For each render target, a ROP unit uses the associated render target sample mask to select covered samples included in the pixel. Subsequently, the ROP unit uses the render target-specific color value to update the selected samples in the render target, thereby achieving sample-level color granularity.

Abstract: A reshift unit within a computer system is configured to store repair information associated with random-access memory (RAM) modules that reside in different power regions. When one or more RAM modules in a given power region need to be repaired, the reshift unit identifies a portion of the repair information that is relevant to those RAM modules. The reshift unit then transmits that portion to the RAM modules, thereby repairing those RAM modules. Accordingly, RAM modules in a given power region can be repaired independently of RAM modules in other power regions. Advantageously, RAM modules can be repaired between cold boots without implementing the slow repair procedure performed by the fuse block during cold boot.

Abstract: One embodiment of the present invention includes techniques for processing a multi-resolution hierarchy, where an application configures a ROP unit to render all the levels included in the multi-resolution hierarchy to a single composite render target. The ROP unit renders memory pages to the composite render target in pitch order. In contrast, the texture unit accesses the composite render target with memory pages in pitch order for each level of the hierarchy. The application configures the MMU to ensure that the composite render target is correctly interpreted by the texture unit. Notably, the MMU translates ROP unit virtual addresses and texture unit virtual addresses using different mapping strategies to the same physical address space. One advantage of the disclosed embodiments is that rendering to the multi-resolution hierarchy does not require the CPU to execute the state parameter changes that are associated with rendering the different hierarchical levels using prior-art techniques.

Abstract: A method includes initiating, through an interface of a data processing device, generation of one or more excerpt(s) of a video sequence associated with a video file stored in a memory of the data processing device. The method also includes automatically reading, through a processor of the data processing device communicatively coupled to the memory, video frames of the video file corresponding to the one or more excerpt(s) and reference video frames thereof in accordance with the initiation through the interface. Further, the method includes decoding, through the processor, the video frames of the video file corresponding to the one or more excerpt(s) and the reference video frames thereof following the automatic reading for rendering thereof on the data processing device.

Abstract: A graphics processing subsystem includes one or more memory devices and two or more graphics processing units (GPU). The graphics processing units each include a memory interface. A first sub-set of the memory interface of the first graphics processing unit communicatively couples the first graphics processing unit to the first memory device. A first sub-set of the memory interface of the second graphics processing unit is connected to a second sub-set of the memory interface of the first graphics processing unit.

Abstract: A method includes executing an instance of a process on a data processing device, and controlling configuration of a display unit, a processor, a memory and/or a power supply of the data processing device through a user interface provided by the process and/or an operating system executing on the data processing device based on continued execution of the instance of the process. The method also includes providing a capability to automatically backup, through the processor in conjunction with a driver component associated with the display unit, the processor and/or the power supply, settings related to one or more specific parameter(s) of the display unit, a screen of the display unit, the processor, the memory, an algorithm executing on the processor and/or the power supply of the data processing device through the user interface as a non-system file to the memory and/or a storage device external to the data processing device.

Abstract: One embodiment of the present invention sets forth a technique for partitioning a predecessor thread program into sub-programs and dynamically spawning a thread grid of the sub-programs based on the outcome of a conditional statement in the predecessor thread program. The programming instructions for the predecessor thread program are analyzed to assess the benefit of partitioning the thread program at a conditional statement into sub-programs. If the predecessor thread program is partitioned, then each branch of the conditional statement may be used to form a separate sub-program. Predicate tables are populated at the predecessor thread program run-time to establish which possible instances of the thread sub-programs should be spawned in subsequent execution phases.

Abstract: Aspects of performing smooth backwards playback in a DVD system are described. The aspects include reconstructing frame data for every frame in a set of frames of an original playback, the set of frames preceding a currently displayed frame. Further included is the utilization of at least seven frame buffers to store frame data during the reconstructing step. The reconstructed frame data is then displayed in reverse order of the original playback for the set of frames.

Abstract: An apparatus comprising: a first transceiver arranged to communicate over a wireless network, the first transceiver comprising a first clock; and a second transceiver arranged to communicate other than by said wireless network, the second transceiver comprising a second clock. The second sends a request signal to the first transceiver. In response, the first transceiver transitions from a first mode to a second mode and provides to the second transceiver a response signal for calibrating the second clock relative to the first clock. In the first mode the first transceiver performs zero or more calibrations of the first clock relative to the wireless network, and in the second mode the first transceiver performs at least one additional calibration of the first clock relative to the wireless network, the response signal being based on the at least one additional calibration.

Abstract: A device compiler and linker is configured to group instructions into different strands for execution by different threads based on the dependence of those instructions on other, long-latency instructions. A thread may execute a strand that includes long-latency instructions, and then hardware resources previously allocated for the execution of that thread may be de-allocated from the thread and re-allocated to another thread. The other thread may then execute another strand while the long-latency instructions are in flight. With this approach, the other thread is not required to wait for the long-latency instructions to complete before acquiring hardware resources and initiating execution of the other strand, thereby eliminating at least a portion of the time that the other thread would otherwise spend waiting.

Abstract: The description is directed to systems and methods for rotating the image displayed on an electronic device. The data associated with the displayed image is stored in memory locations, typically in a matrix of rows and columns of pixel data. A position sensor detects the rotational position of the device, and this position is used to control the manner in which data is read from the image model. Specifically, data is read from the image model using a read sequence that varies with the detected position of the device, thereby eliminating the need for making additional copies of the image data to account for device rotation.