Patents Assigned to NVidia
  • Patent number: 8949576
    Abstract: An apparatus for processing operations in an adaptive computing environment is provided. The adaptive computing environment including at least one processing node. A node includes a memory configured to receive and store data. The data is received from a programmable interconnection network and stored. The node also includes an execution unit configured to perform a signal processing operation. The operation is performed using data retrieved from the memory and an output result is generated. The output result may be used for further computations or sent directly to the programmable interconnection network for transfer to another processing node in the adaptive computing environment.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: February 3, 2015
    Assignee: NVIDIA Corporation
    Inventor: Eugene B. Hogenauer
  • Patent number: 8949645
    Abstract: Embodiments related to controlling power distribution within a microprocessor are provided. In one example, a microprocessor comprising a power supply is provided. The example microprocessor also includes a plurality of power gate zones configured to receive power from the power supply, each power gate zone including a plurality of power gates, where the power gates within any given one of the power gate zones are controlled by the microprocessor independently of its control of power gates within any other of the power gate zones. The example microprocessor is operative to cause power initially to be supplied to a first power gate in a first one of the power gate zones, power then to be supplied to a second power gate in a second one of the power gate zones, and power then to be supplied to a third power gate in the first one of the power gate zones.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Nvidia Corporation
    Inventors: Sagheer Ahmad, Tezaswi Raja
  • Patent number: 8949497
    Abstract: In an apparatus according to one embodiment of the present disclosure, a communications link comprises a first device and a second device communicating with each other via the communications link at a plurality of different speeds. However, prior to communicating via the communications link for the first time at a second speed, the first device and second device complete a first training cycle at the second speed. Further, during this first training cycle for the second speed, the first training cycle for the second speed will pause before the first training cycle at the second speed completes, and the first device and second device communicate at a first speed for a period of time before returning to the paused first training cycle at the second speed. When the paused first training cycle for the second speed continues, the first training cycle for the second speed will continue where it had paused.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: February 3, 2015
    Assignee: NVIDIA Corporation
    Inventors: Michael Hopgood, Wei-Je Huang, Mark Taylor, Hitendra Dutt, David Wyatt, Vishal Mehta
  • Patent number: 8948817
    Abstract: A wireless serving communication unit comprises a signal processor, for receiving and processing a signal to be broadcast, and a number of transmitters operably coupled to the signal processor, for transmitting the broadcast signal in a plurality of sectorised cells to a wireless subscriber communication unit. The wireless serving communication unit comprises logic to replicate the processed signal into a plurality of replicated signals and logic introduce one or more delay(s) to one or more of the replicated processed signals, such that replicated broadcast signals having different delays are transmitted from a plurality of sectorised cells to one or more wireless subscriber communication unit.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: February 3, 2015
    Assignee: Nvidia Corporation
    Inventors: Peter Bruce Darwood, Timothy Wilkinson
  • Patent number: 8949841
    Abstract: A streaming multiprocessor (SM) in a parallel processing subsystem schedules priority among a plurality of threads. The SM retrieves a priority descriptor associated with a thread group, and determines whether the thread group and a second thread group are both operating in the same phase. If so, then the method determines whether the priority descriptor of the thread group indicates a higher priority than the priority descriptor of the second thread group. If so, the SM skews the thread group relative to the second thread group such that the thread groups operate in different phases, otherwise the SM increases the priority of the thread group. f the thread groups are not operating in the same phase, then the SM increases the priority of the thread group. One advantage of the disclosed techniques is that thread groups execute with increased efficiency, resulting in improved processor performance.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: February 3, 2015
    Assignee: NVIDIA Corporation
    Inventors: Jack Hilaire Choquette, Olivier Giroux, Robert J. Stoll, Gary M. Tarolli, John Erik Lindholm
  • Patent number: 8948167
    Abstract: One embodiment of the present invention is a control unit for distributing packets of work to one or more consumer of works. The control unit is configured to assign at least one processing domain from a set of processing domains to each consumer included in the one or more consumers, receive a plurality of packets of work from at least one producer of work, wherein each packet of work is associated with a processing domain from the set of processing domains, and a first packet of work associated with a first processing domain can be processed by the one or more consumers independently of a second packet of work associated with a second processing domain, identify a first consumer that has been assigned the first processing domain, and transmit the first packet of work to the first consumer for processing.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: February 3, 2015
    Assignee: NVIDIA Corporation
    Inventors: Lacky V. Shah, Sean J. Treichler, Abraham B. de Waal
  • Patent number: 8949652
    Abstract: In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: February 3, 2015
    Assignee: Nvidia Corporation
    Inventor: Chi Keung Lee
  • Patent number: 8949541
    Abstract: A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: February 3, 2015
    Assignee: NVIDIA Corporation
    Inventors: David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, James Roberts, John H. Edmondson
  • Patent number: 8947137
    Abstract: Presented systems and methods facilitate efficient reset operation. In one embodiment, a system comprises a core domain portion an I/O domain portion and a core reset I/O by-pass component. The core domain portion is configured to operate at a nominal core domain voltage level. The I/O domain portion configured to operate at a nominal I/O domain voltage level. The core reset I/O by-pass component configured to forward a reset indication to the core domain independent of the I/O domain. In one exemplary implementation the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage, wherein the high domain is voltage higher than the core domain voltage level.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: February 3, 2015
    Assignee: NVIDIA Corporation
    Inventor: Alan Li
  • Patent number: 8947432
    Abstract: One embodiment of the invention sets forth a mechanism for interleaving consecutive display frames rendered at complementary reduced resolutions. The GPU driver configures a command stream associated with a frame received from a graphics application for reduced frame rendering. The command stream specifies a nominal resolution at which the frame should be rendered. The reduced resolution associated with the frame is determined based on the reduced resolution of an immediately preceding frame (i.e., the complementary reduced resolution), if one exists, or on GPU configuration information. The GPU driver then modifies the command stream to specify the reduced resolution. The GPU driver also inserts an upscale command sequence specifying the nominal resolution into the command stream. Once the command stream is configured in such a manner, the GPU driver transmits the command stream to the GPU for reduced rendering.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: February 3, 2015
    Assignee: NVIDIA Corporation
    Inventors: Jonathan Bakdash, Qi Mo, David Luebke, Douglas A. Voorhies
  • Publication number: 20150030070
    Abstract: A method includes determining that a reference video frame of a predicted frame or a bi-predicted frame, corresponding to a point in time of beginning of a non-sequential playback of video data and currently being decoded, is unavailable or corrupt. The method also includes determining if a reference video frame utilized most recently with reference to the point in time to decode another video frame is available in the memory. Further, the method includes decoding the predicted frame or the bi-predicted frame based on employing the reference video frame utilized most recently as a reference video frame thereof if the reference video frame utilized most recently is determined to be available; if not, the decoding is based on employing a video frame of the video data in the memory temporally closest to the point in time as the reference video frame of the predicted frame or the bi-predicted frame.
    Type: Application
    Filed: July 29, 2013
    Publication date: January 29, 2015
    Applicant: NVIDIA Corporation
    Inventors: Shivram Latpate, Masood Shaikh
  • Patent number: 8942474
    Abstract: A method for performing indexing in an image decoder. The method includes identifying a tile in an image, wherein the image comprises a plurality of tiles, and wherein each tile includes color data associated with a plurality of pixels. The method includes asymmetrically providing a plurality of indices throughout the tile. The method includes identifying a pixel in the tile. The method also includes determining a corresponding rectangular grid that includes the pixel, wherein the corresponding rectangular grid comprises at least one indices in a group of indices. The method includes determining an index for the pixel by bilinearly filtering the group of indices that is associated with the corresponding rectangular grid, wherein the filtering is performed in relation to the pixel.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 27, 2015
    Assignee: Nvidia Corporation
    Inventors: Eric Sovelen Werness, Walter E. Donovan, Cass Watson Everitt
  • Patent number: 8943448
    Abstract: A hardware model database is identified which stores a graph-based common representation of a hardware design that includes hardware module nodes each representative of a unique module of the hardware design and associated with one or more instances of the unique module. Additionally, a signal dump resulting from a simulation of a logic code model of the hardware design is identified. Each instance of each unique module is identified using the hardware model database, and for each assertion condition included therein, a corresponding value for the assertion condition is determined from the signal dump. Further, a construct of the hardware design corresponding to each instance of each unique module is conditionally displayed by a debugger application, based on the determined values of the corresponding assertion conditions included in the instance of the unique module.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventor: Robert Anthony Alfieri
  • Patent number: 8943091
    Abstract: A system, method, and computer program product are provided for performing a string search. In use, a first string and a second string are identified. Additionally, a string search is performed, utilizing the first string and the second string.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: Jacopo Pantaleoni, David Tarjan
  • Patent number: 8943584
    Abstract: A method for providing an operating system access to devices, including enumerating hardware devices and virtualized devices, where resources associated with a first hardware device are divided into guest physical resources creating a software virtualized device, and multiple instances of resources associated with a second hardware device are advertised thereby creating a hardware virtualized device. First and second permission lists are generated that specify which operating systems are permitted to access the software virtualized device and the hardware virtualized device, respectively. First and second sets of virtual address maps are generated, where each set maps an address space associated with either the software virtualized device or the hardware virtualized device into an address space associated with each operating system included in the corresponding permission list.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: Brad W. Simeral, Michael Brian Cox
  • Patent number: 8943559
    Abstract: A method of authenticating access to an electrical device. The method comprises comparing, at an electronic processor, one or more patterns of temporal or physical properties, associated with an access entry string, to a non-transitory electronic profile data base of ranges of the corresponding patterns, from previously approved access entry strings. The method also comprises approving or denying at the electronic processor, the access entry string. The access entry string is approved if the one or more patterns falls within the respective range of the corresponding patterns in the profile data base. The access entry string is denied if the one or more patterns falls outside the respective range of the corresponding patterns in the profile data base.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: January 27, 2015
    Assignee: Nvidia Corporation
    Inventor: Andrew Fear
  • Patent number: 8941669
    Abstract: Frames are rendered by multiple graphics processors (GPUs), which may be heterogeneous. Graphics processors split the execution of the command in a push buffer of a frame. One GPU begins rendering a frame, and a second GPU takes over rendering that frame after the second GPU is done rendering a previous frame. The second GPU may then begin rendering a subsequent frame.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventor: Henry P. Moreton
  • Patent number: 8941594
    Abstract: An interface, apparatus, circuit and method for interfacing with an electronic device, such as a cellular telephone, are disclosed. The interface includes a key pad with a number of keys, each operable for providing a unique input to the electronic device, and a actuator for selectively actuating one or more of the keys. A controller, coupled to the key pad, scans the keys according to a mode of operation of the electronic device. A mode selector, operable with the controller, selects a first or second operating mode. In the first, useful for instance in performing telephonic functions, each key provides its unique input discretely. In the second mode, useful for instance for providing a game related function, certain of the keys are selectively chorded to function for providing their respective inputs together, effectively simultaneously, according to a manipulation of the actuator by the user.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: January 27, 2015
    Assignee: Nvidia Corporation
    Inventor: William E. Rehbock
  • Patent number: 8941653
    Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: Steven E. Molnar, Emmett M. Kilgariff, John S. Rhoades, Timothy John Purcell, Sean J. Treichler, Ziyad S. Hakura, Franklin C. Crow, James C. Bowman
  • Patent number: 8943457
    Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: Amit Dinesh Sanghani, Punit Kishore