Patents Assigned to NVidia
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Publication number: 20150042669Abstract: The description is directed to systems and methods for rotating the image displayed on an electronic device. The data associated with the displayed image is stored in memory locations, typically in a matrix of rows and columns of pixel data. A position sensor detects the rotational position of the device, and this position is used to control the manner in which data is read from the image model. Specifically, data is read from the image model using a read sequence that varies with the detected position of the device, thereby eliminating the need for making additional copies of the image data to account for device rotation.Type: ApplicationFiled: August 8, 2013Publication date: February 12, 2015Applicant: NVIDIA CorporationInventors: Mark Van Nostrand, Sarika Bhimkaran Khatod
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Publication number: 20150043698Abstract: Systems and methods for stabilizing clock data recovery (CDR) by filtering the abrupt phase shift associated with data pattern transition in the input signal. The CDR circuit includes a data pattern detector coupled to a data pattern filter. The data pattern detector is capable of detecting the data patterns of the input signal. Accordingly, the data pattern filter can selectively generate a filter indication indicating to freeze or suppress the CDR phase caused by data pattern transition. The filter indication can be incorporated to a phase error signal, a gain function, and/or the control voltage driving the VCO.Type: ApplicationFiled: August 12, 2013Publication date: February 12, 2015Applicant: NVIDIA CORPORATIONInventors: Yu CHANG, Huabo CHEN, Hakki OZGUC, Michael HOPGOOD
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Publication number: 20150042553Abstract: An aspect of the present invention proposes a solution to allow a dynamic adjustment of a performance level of a GPU based on the user observed screen area. According to one embodiment, a user's focus in one or more display panels is determined. The GPU that performs rendering for that region and/or display panel will dynamically adjust (i.e., increase) the level of performance in response to the user's focus, whereas all other GPUs (e.g., the GPUs that perform rendering for other regions/display panels) will experience a reduced level of performance.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Applicant: NVIDIA CorporationInventor: Andrew Mecham
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Publication number: 20150046662Abstract: A system, method, and computer program product are provided for coalescing memory access requests. A plurality of memory access requests is received in a thread execution order and a portion of the memory access requests are coalesced into memory order, where memory access requests included in the portion are generated by threads in a thread block. A memory operation is generated that is transmitted to a memory system, where the memory operation represents the coalesced portion of memory access requests.Type: ApplicationFiled: August 6, 2013Publication date: February 12, 2015Applicant: NVIDIA CorporationInventors: Steven James Heinrich, Ramesh Jandhyala, Bengt-Olaf Schneider
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Publication number: 20150042664Abstract: A device for processing graphics data includes a plurality of graphics processing units. Each graphics processing unit may correspond to a virtualized operating system. Each graphics processing unit may include a configuration register indicating a 3D class code and a command register indicating that I/O cycle decoding is disabled. The device may be configured to transmit a configuration register value to a virtualized operating system indicating a VGA-compatible class code. The device may be configured to transmit a command register value to the virtualized operating system that indicates that I/O cycle decoding is enabled. In this manner, legacy bus architecture of the device may not limit the number of graphics processing units deployed in the device.Type: ApplicationFiled: September 13, 2013Publication date: February 12, 2015Applicant: NVIDIA CorporationInventors: Andrew CURRID, Franck DIARD, Chenghuan JIA, Parag KULKARNI
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Publication number: 20150046612Abstract: A packaged memory device includes a semiconductor interposer, a first memory stack, a second memory stack, and a buffer chip that are all coupled to the semiconductor interposer. The first memory stack and the second memory stack each include multiple memory chips that are configured as a single stack. The buffer chip is electrically coupled to the first memory stack via a first data bus, electrically coupled to the second memory stack via a second data bus, and electrically coupled to a processor data bus that is configured for transmitting signals between the buffer chip and a processor chip. Such a memory device can have high data capacity and still operate at a high data transfer rate in an energy efficient manner.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Applicant: NVIDIA CORPORATIONInventor: Alok GUPTA
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Publication number: 20150042652Abstract: A system, method, and computer program product are provided for simulating light transport. In operation, a distribution function is decomposed utilizing a technique for sampling from a probability distribution (e.g. the Alias Method, etc.). Additionally, light transport associated with at least one scene is simulated utilizing information associated with the decomposed distribution function.Type: ApplicationFiled: August 8, 2013Publication date: February 12, 2015Applicant: NVIDIA CorporationInventors: Alexander Keller, Ken Patrik Dahm, Nikolaus Binder
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Publication number: 20150042672Abstract: A parallel multicolor ILU factorization preconditioner processor and a method of computing an ILU preconditioning matrix. One embodiment of the preconditioning processor having parallel computing pipelines includes: (1) a graph coloring circuit operable to identify parallelisms in a sparse linear system, (2) an ILU computer configured to employ the parallel computing pipelines according to the parallelisms to: (2a) determine a sparsity pattern for an ILU preconditioning matrix, and (2b) compute non-zero elements of the ILU preconditioning matrix according to the sparsity pattern, and (3) a memory communicably couplable to the parallel computing pipelines and configured to store the ILU preconditioning matrix.Type: ApplicationFiled: August 8, 2013Publication date: February 12, 2015Applicant: Nvidia CorporationInventors: Robert Strzodka, Julien Demouth, Patrice Castonguay
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Patent number: 8951814Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.Type: GrantFiled: January 22, 2013Date of Patent: February 10, 2015Assignee: NVIDIA CorporationInventors: Brian S. Schieck, Howard Lee Marks
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Patent number: 8952736Abstract: A phased lock loop (PLL) including a retimer unit, rotator unit, and clock selection unit. The retimer unit is configured for sampling a divided clock generated by a divide-by-N unit with a plurality of phases of an oscillator clock generated by a ring oscillator to generate a plurality of phase shifted divide-by-N clocks. The rotator unit is configured for selectively rotating through the plurality of phase shifted divide-by-N clocks based on a constant phase shift interval, wherein the rotator unit controls a clock selection unit to produce a single output phase selected from a plurality of generated divide-by-N clock phases.Type: GrantFiled: October 9, 2013Date of Patent: February 10, 2015Assignee: NVIDIA CorporationInventors: Ken Evans, Bhupendra Ahuja
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Patent number: 8952705Abstract: Systems and methods for transition delay measuring are presented. A transition delay measuring method can include oscillating a signal between states and tracking an indication associated with an isolated attribute of the transitions between the states. Oscillations can include asymmetric transitions between the states and the tracked isolated attribute can be a delay in completing transitions between the states in one direction or vice versa. The asymmetric transitions can include transitions between the first state and the second state that are faster than slower transitions between the second state and the first state or vice versa. The tracked indication can be utilized in analysis of the isolated transition delay characteristics. The results can be utilized in analysis of various further features and characteristics (e.g., examination of leakage current related power consumption, timing of asymmetric operation, etc.). The analysis can include examination of fabrication process and operating parameters.Type: GrantFiled: November 1, 2011Date of Patent: February 10, 2015Assignee: Nvidia CorporationInventors: Ilyas Elkin, Wojciech Jakub Poppe
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Publication number: 20150036695Abstract: Systems and methods for multiplexing audio/video data and generating transport streams for WiFi network with reduced latency for real time playback at a remote device. A virtual presentation clock reference (PCR) representing a scheduled transmission time of a transport stream packet at a transport stream multiplexer is calculated based on the network transmission rate and generation of the data packets. The virtual PCR is compared with the corresponding system PCR to derive a time difference. Based on the time difference, the transport stream multiplexer is configured to adaptively drop packets or throttle packet generation so as to synchronize the playback of audio/video data on a sink device with the generation of interleaved audio/video packets.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: NVIDIA CorporationInventors: Rahul GOWDA, Olivier LAPICQUE, Thomas MEIER
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Publication number: 20150036020Abstract: A method for storing digital images is presented. The method comprises accessing a first image. It further comprises capturing at least one second image. Further, it comprises storing metadata associated with the at least one second image in at least one field within a file format of the first image, wherein the file format defines a structure for the image, and wherein the at least one field is located within an extensible segment of the file format. In one embodiment, the at least one second image is an image that is intermediate in relation to the first image, wherein the at least one second image is selected from a group consisting of: intermediate HDR images; RAW Bayer image data; RGB image data; RAW images; multiple exposures captured to produce a single final image.Type: ApplicationFiled: August 5, 2013Publication date: February 5, 2015Applicant: NVIDIA CorporationInventors: Patrick Shehane, Guanghua Zhang
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Publication number: 20150035842Abstract: A method includes providing an input port and/or an output port directly interfaced with a Graphics Processing Unit (GPU) of a data processing device further including a Central Processing Unit (CPU) to enable a corresponding reception of input data and/or rendering of output data therethrough. The method also includes implementing a voice/audio processing engine in the data processing device. Further, the method includes performing voice/audio related processing of the input data received through the input port and/or voice/audio related processing of data in the data processing device to realize the output data based on executing the voice/audio processing engine solely through the GPU.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicant: NVIDIA CorporationInventor: Mahesh Sambhaji Jadhav
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Publication number: 20150036875Abstract: Embodiments of the present invention enable mobile devices to behave as a dedicate remote control for different target devices through camera detection of a particular target device and autonomous execution of applications linked to the detected target device. Also, when identical target devices are detected, embodiments of the present invention may be configured to use visual identifiers and/or positional data associated with the target device for purposes of distinguishing the target device of interest. Additionally, embodiments of the present invention are capable of being placed in a surveillance mode in which camera detection procedures are constantly performed to locate target devices. Embodiments of the present invention may also enable users to engage this surveillance mode by pressing a button located on the mobile device. Furthermore, embodiments of the present invention may be trained to recognize target devices.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: NVIDIA CorporationInventor: Guillermo SAVRANSKY
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Publication number: 20150039621Abstract: A method for storing digital images is presented. The method includes capturing an image using a digital camera system. It also comprises capturing metadata associated with the image or a moment of capture of the image. Further, it comprises storing the metadata in at least one field within a file format, wherein the file format defines a structure for the image, and wherein the at least one field is located within an extensible segment of the file format. In one embodiment, the metadata is selected from a group that comprises audio data, GPS data, time data, related image information, heat sensor data, gyroscope data, annotated text, and annotated audio.Type: ApplicationFiled: August 5, 2013Publication date: February 5, 2015Applicant: NVIDIA CorporationInventors: Peter Mikolajczyk, Patrick Shehane, Guanghua Gary Zhang
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Publication number: 20150039662Abstract: A fused floating-point multiply-add element includes a multiplier that generates a product, and a shifter that shifts an addend within a narrow range. Interpreting logic analyzes the magnitude of the addend relative to the product and then causes logic arrays to position the shifted addend within the left, center, or right portions of a composite register depending in the magnitude of the addend relative to the product. The interpreting logic also forces other portions of the composite register to zero. When the addend is zero, the interpreting logic forces all portions of the composite register to zero. Final combining logic then adds the contents of the composite register to the product.Type: ApplicationFiled: August 5, 2013Publication date: February 5, 2015Applicant: NVIDIA CORPORATIONInventors: Srinivasan IYER, David Conrad TANNENBAUM, Stuart F. OBERMAN, Ming (Michael) Y. SIU
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Publication number: 20150035999Abstract: A method for sharing digital photos securely is presented. The method includes capturing image data using a digital camera system. It also includes encrypting the image data using an encryption key to produce encrypted image data. Further, it comprises storing metadata associated with the encrypting in at least one field within a file format, wherein the file format defines a structure for storing the encrypted image data, and wherein the at least one field is located within an extensible segment of the file format. Finally, it comprises transmitting the encrypted image data to a recipient.Type: ApplicationFiled: August 5, 2013Publication date: February 5, 2015Applicant: NVIDIA CorporationInventors: Patrick Shehane, Guanghua Zhang
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Patent number: 8947430Abstract: A method for rendering a particle-based fluid surface includes generating a depth image of a plurality of particles which form a fluid surface, and smoothing the depth image to generate a smoothed depth image. From the smoothed depth image, a smoothed surface position and a smoothed surface normal for each of a plurality of pixels included within the smoothed depth image is determined, and a shaded surface of the fluid is rendered as a function of the smoothed surface positions and the smoothed surface normals.Type: GrantFiled: February 26, 2010Date of Patent: February 3, 2015Assignee: NVIDIA CorporationInventors: Simon Green, Miguel Sainz, Wladimir Van Der Laan
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Patent number: 8947444Abstract: A data structure that includes pointers to vertex attributes and primitive descriptions is generated and then processed within a general processing cluster. The general processing cluster includes a vertex attribute fetch unit that fetches from memory vertex attributes corresponding to the vertices defined by the primitive descriptions.Type: GrantFiled: December 9, 2008Date of Patent: February 3, 2015Assignee: NVIDIA CorporationInventors: Ziyad S. Hakura, Emmett M. Kilgariff, Michael C. Shebanow, James C. Bowman, Philip Browning Johnson, Johnny S. Rhoades, Rohit Gupta