Abstract: A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.

Abstract: A system, method, and computer program product for generating high-dynamic range image data is disclosed. The method includes the steps of receiving image sensor data from an interleaved image sensor. The interleaved the image sensor includes a first portion of pixels exposed for a first exposure time and a second portion of pixels exposed for a second exposure time that is shorter than the first exposure time. The method further includes the steps of identifying a first subset of pixels in the second portion having an intensity value above a first threshold value, identifying a second subset of pixels in the first portion having an intensity value below a second threshold value, and generating high-dynamic range (HDR) data based on the first subset and the second subset.

Abstract: A streaming multiprocessor (SM) in a parallel processing subsystem schedules priority among a plurality of threads. The SM retrieves a priority descriptor associated with a thread group, and determines whether the thread group and a second thread group are both operating in the same phase. If so, then the method determines whether the priority descriptor of the thread group indicates a higher priority than the priority descriptor of the second thread group. If so, the SM skews the thread group relative to the second thread group such that the thread groups operate in different phases, otherwise the SM increases the priority of the thread group. f the thread groups are not operating in the same phase, then the SM increases the priority of the thread group. One advantage of the disclosed techniques is that thread groups execute with increased efficiency, resulting in improved processor performance.

Abstract: A web-based graphics development system for developing a graphics application and a method of debugging a graphics application. One embodiment of the graphics development system includes: (1) a web server application configured to host at least one graphics library and linkable to the graphics application, and (2) a client configured to gain access to and interact with the graphics application through a web browser application couplable to the web server application over a network.

Abstract: A mobile computing device comprising a noncontact location sensor operable to detect the presence of an input object that enters a detectable region proximate to the touch screen panel. The sensor can produce location signals representing the location of the input means relative to a plurality of virtual input characters. Based on the location signals, a target virtual character can be identified and magnified to a more recognizable and accessible size before a user makes an input selection. Optionally, a series of virtual characters adjacent to the target character may also be magnified to facilitate the user to locate the desired character and improve user input accuracy. The noncontact location sensor may comprise an infrared location sensor, an optical sensor, a magnetic sensor or a combination thereof.

Abstract: A method for dynamically adjusting a frame buffer resolution, the method comprising calculating a target scaling factor based upon a calculated average frame rate and incrementally changing a current scaling factor to reach the target scaling factor. The method includes calculating the target scaling factor based upon the average frame rate and a current scaling factor. The method includes adjusting a resolution of a frame of data rendered to the frame buffer according to the current scaling factor.

Abstract: One or more embodiments of the present invention may include a body comprising a user interface, wherein the user interface is operable to be configured for a first interactive media device and a second interactive media device. The one or more embodiments may further include memory operable to store a plurality of user interface configurations, wherein a first user interface configuration corresponds to the first interactive media device and the second interactive media device, and wherein the memory is further operable to store a software application state. The one or more embodiments may additionally include a communication interface operable to communicatively couple with the first interactive media device and the second interactive media device, wherein the communication interface is operable to send user inputs from the user interface to the first interactive media device and the second interactive media device.

Abstract: A system and method for decompressing compressed data (e.g., in a frame buffer) and optionally recompressing the data. The method includes determining a portion of an image to be accessed from a memory and sending a conditional read corresponding to the portion of the image. In response to the conditional read, an indicator operable to indicate that the portion of the image is uncompressed may be received. If the portion of the image is compressed, in response to the conditional read, compressed data corresponding to the portion of the image is received. In response to receiving the compressed data, the compressed data is uncompressed into uncompressed data. The uncompressed data may then be written to the memory corresponding to the portion of the image. The uncompressed data may then be in-place compressed for or during subsequent processing.

Abstract: A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level.

Abstract: Provided is an online application distribution system. The online application distribution system, in this aspect, includes an application reservoir. The online application distribution system, in this aspect, further includes a beta test manager configured to determine if a user associated with the system will participate in beta testing for a beta application in the application reservoir.

Abstract: In one embodiment, a method for identifying and replacing code translations that generate spurious fault events includes detecting, while executing a first native translation of target instruction set architecture (ISA) instructions, occurrence of a fault event, executing the target ISA instructions or a functionally equivalent version thereof, determining whether occurrence of the fault event is replicated while executing the target ISA instructions or the functionally equivalent version thereof, and in response to determining that the fault event is not replicated, determining whether to allow future execution of the first native translation or to prevent such future execution in favor of forming and executing one or more alternate native translations.

Abstract: A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.

Abstract: A system, process, and computer program product are provided for identifying a faulty processing unit. A shader program that configures a plurality of processing units to generate data is executed and the data is compared with verification data to produce a test result. The test result is examined to identify a faulty processing unit of the plurality of processing units, where a unique identifier corresponding to each processing unit is encoded into the data generated by the respective processing unit.

Abstract: One embodiment of the present invention sets forth a technique for mid-primitive execution preemption. When preemption is initiated no new instructions are issued, in-flight instructions progress to an execution unit boundary, and the execution state is unloaded from the processing pipeline. The execution units within the processing pipeline, including the coarse rasterization unit complete execution of in-flight instructions and become idle. However, rasterization of a triangle may be preempted at a coarse raster region boundary. The amount of context state to be stored is reduced because the execution units are idle. Preempting at the mid-primitive level during rasterization reduces the time from when preemption is initiated to when another process can execute because the entire triangle is not rasterized.

Abstract: Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during the execution of the thread array. Also in these techniques, the execution units execute a trap handling routine that includes a context switch. The execution units perform this context switch for at least one of the execution units as part of the trap handling routine while allowing the remaining execution units to exit the trap handling routine before the context switch. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.

Abstract: A system and method of scalable resolution display are presented. Embodiments of the present invention are operable to partition the native resolution (e.g., available pixel density) of a high pixel density display screen into multiple display regions (windows) in a manner such that each partitioned display region is capable of independently displaying scaled output with respect to its allotted native resolution. As such, both high pixel count images and “low” pixel count images may be displayed simultaneously within the same high pixel density display screen in a manner that enhances the user's visual experience.

Abstract: An AMOLED display panel comprising a plurality of color elements in each pixel with each of the color elements comprising a discrete plurality of illuminating units associated with a plurality of transistors operating in a binary mode. The plurality of illuminating units have different sizes in accordance with 2n size, where n is the illuminating unit's number. n may also be the bit position of the bit line that controls the illuminating unit. The collective luminance of each color element can be digitally controlled by selectively activating a combination of the discrete illuminating units to their nominal luminance. The discrete plurality of illuminating units in each pixel may be directly controlled by RGB pixel data without the requirement for digital analog conversion.

Abstract: One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two.

Abstract: A touch screen system includes a touch screen that provides touch information in response to a touch event. The touch screen system also includes a rapid response display controller having a reactive interpretation unit that provides an initial display representation of the touch information and a reactive feedback unit that provides the initial display representation to the touch screen for an initial display. The touch screen system further includes a routine response display controller that additionally receives the touch information and provides a final display representation of the touch information to the touch screen for a final display. A method of touch screen display management is also included.

Abstract: A multiplexer tree operable to control an output a sequence of data stored in a plurality of storage units in accordance with a non-linear address sequence that has less bit transition counts than a linear address sequence. The non-linear address sequence is provided to the selection inputs of the multiplexer tree and causes the levels having greater numbers of multiplexers to toggle less frequently than the levels having smaller numbers of multiplexers. The non-linear address sequence may comprise a Gray code sequence where every two adjacent addresses differ by a single bit. The non-linear address sequence may be optimized to minimize transistor switching in the multiplexer tree.