Abstract: A method for transferring graphics data includes receiving graphics data in the system memory. The graphics data may be loaded into system memory by and application from a mass storage device. One or more graphics commands associated with the graphics data may also be received. The graphics commands may also be received from the application. The graphics data in system memory is compressed in response to receipt of the one or more graphics commands before the graphics data is transferred to a discrete graphics processing unit. The one or more received graphics commands are transferred to the discrete graphics processing unit. The one or more graphics commands include an operation to copy the compressed graphics data to the discrete graphics processing unit. The compressed graphics data is copied from the system memory to memory of the graphics processing. The compressed graphics data is then decompressed by the graphics processing unit.

Abstract: One embodiment of the present invention sets forth a system that includes a detection device and a processor. The detection device is configured to sense that a handheld device has not been placed on or near a surface. In response to sensing that the handheld device has not been placed on or near a surface, the detection device is configured to transmit an indicator to the processor. The processor is configured to receive a first audio signal, and determine that the handheld device has not been placed on or near a surface by receiving the indicator from the detection device. In response to determining that the handheld device has not been placed on or near a surface, the processor is further configured to apply a compensating function to the first audio signal to generate a second audio signal, and transmit the second audio signal to a speaker.

Abstract: A system and method for performing computer algorithms. The system includes a graphics pipeline operable to perform graphics processing and an engine operable to perform at least one of a correlation determination and a convolution determination for the graphics pipeline. The graphics pipeline is further operable to execute general computing tasks. The engine comprises a plurality of functional units operable to be configured to perform at least one of the correlation determination and the convolution determination. In one embodiment, the engine is coupled to the graphics pipeline. The system further includes a configuration module operable to configure the engine to perform at least one of the correlation determination and the convolution determination.

Abstract: A system and method for distributed processing, rendering, and displaying of content. A first client request is received from a first client of a plurality of clients. The first client request is authenticated from the first client of the plurality of clients. A first data stream type is determined, based on the first client request, to establish with the first client of the plurality of clients. The first session comprising the first data type is established, based on a determination of the first data stream type, with the first client of the plurality of clients. The data of the first stream data type is provided for the first session to the first client of the plurality of clients.

Abstract: A method includes monitoring data communicated over a bus and determining that the data is communicated between a peripheral device and a client device. The method also includes sending the data in an unaltered form, and an identifier identifying the peripheral device, to a cloud server, wherein the data is operable to be received by a device driver executing on the cloud server. Another method includes receiving data in an unaltered form and an identifier identifying a peripheral device, wherein the unaltered data is a forwarded communication between the peripheral device and a client device. The method also includes enabling a device driver based on the received identifier. The method also includes executing one or more commands via the device driver, based on the received data.

Abstract: An apparatus including: a receiving module operable to receive video content through a communication network simultaneously from a set of devices; a decoding module operable to decode the received video content from the set of devices into decoded video content; an arranging module operable to combine and arrange the decoded video content into a single video; and a displaying module operable to provide the single video for display on a display device.

Abstract: A system and method for re-factorizing a square input matrix on a parallel processor. In one embodiment, the system includes: (1) a matrix generator operable to generate an intermediate matrix by embedding a permuted form of the input matrix in a zeroed-out sparsity pattern of a combination of lower and upper triangular matrices resulting from a prior LU factorization of a previous matrix having a same sparsity pattern, reordering to minimize fill-in and pivoting strategy as the input matrix and (2) a re-factorizer associated with the matrix generator and operable to use parallel threads to apply an incomplete-LU factorization with zero fill-in on the intermediate matrix.

Abstract: One embodiment of the present invention sets forth a system that includes a detection device and a processor. The detection device is configured to sense that a handheld device has not been placed on or near a surface. In response to sensing that the handheld device has not been placed on or near a surface, the detection device is configured to transmit an indicator to the processor. The processor is configured to receive a first audio signal, and determine that the handheld device has not been placed on or near a surface by receiving the indicator from the detection device. In response to determining that the handheld device has not been placed on or near a surface, the processor is further configured to apply a compensating function to the first audio signal to generate a second audio signal, and transmit the second audio signal to a speaker.

Abstract: Automated methods for correcting the remaining portion of a project schedule in order to reflect actual performance to date are provided. For some embodiments, the remaining schedule is corrected by applying factors that are extrapolated from the actual completion times of project milestones in comparison to the scheduled times for the same milestones. This approach results in a project schedule that is more accurate, and thus enables improved management of the project.

Abstract: A system, method, and computer program product are provided for grouping linearly ordered primitives. In operation, a plurality of primitives are linearly ordered. Additionally, the primitives are grouped. Furthermore, at least one intersection query is performed, utilizing the grouping.

Abstract: One embodiment of the present invention sets forth a technique for subdividing stroked higher-order curved segments into quadratic Bèzier curve segments. Path stroking may be accelerated when a GPU or other processor is configured to perform the subdivision operations. Cubic Bèzier path segments are subdivided into quadratic Bèzier curve segments and other lower-order segments at key features. The quadratic Bèzier curve segments approximate the cubic Bèzier path segments. A variance metric is computed for each quadratic Bèzier curve segment, and when the variance metric indicates that the quadratic Bèzier curve segment deviates by more than a threshold from the corresponding portion of the cubic Bèzier path segment, the quadratic Bèzier curve segment is further subdivided. The path composed of the quadratic Bèzier curve segments is then stroked by rendering hull geometry that encloses the path.

Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors including manufacturing defects, compatibility characteristics, performance requirements, and system health (e.g., the number of components operating properly). Functional component operational behavior is tested and analyzed at various levels of configuration abstraction and component organization (e.g., topological inversion analysis). The testing and analysis can be performed in parallel on numerous functional components. Functional component configuration related information is presented in a graphical user interface (GUI) at various levels of granularity and in real time.

Abstract: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.

Abstract: The graphics co-processing technique includes rendering a frame of red, green, blue (RGB) data on a graphics processing unit on an unattached adapter. The frame of RGB data are converted on the graphics processing unit on the unattached adapter to luminance-color difference (YUV) data. The YUV data is copied from frame buffers of the graphics processing unit on the unattached adapter to buffers in system memory. The YUV data is copied from the buffers in the system memory to texture buffers of a graphics processing unit on a primary adapter. A frame of RGB data is recovered from the YUV data in the texture buffer of the graphics processing unit on the primary adapter. The recovered frame of RGB data may then be presented by the graphics processing unit on the primary adapter on the primary display.

Abstract: A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.

Abstract: A method for tag logic score boarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality of pixels of pixels related to the graphics primitive. The method further includes accounting for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics pipeline and accounting for a completion of parameter evaluation for each of the plurality of pixels as the pixels complete processing in the subsequent stage of the graphics pipeline. Respective tag memory is allocated to track the initiation of parameter evaluation and the completion of parameter evaluation for each of the plurality of pixels.

Abstract: Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists.

Abstract: One embodiment of the present invention sets forth a method, which includes the steps of generating a first rendered image associated with a first application, independently generating a second rendered image associated with a second application, applying a first set of blending weights to the first rendered image to establish a first weighted image, applying a second set of blending weights to the second rendered image to establish a second weighted image, and blending the first weighted image and the second weighted image before scanning out a blended result to a first display device.

Abstract: The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in a manner that maintains the basic functionality of the chip. A chip is tested and a functional component configuration process is performed on the chip based upon results of the testing. If an indication of a defective functional component is received, the functional component is disabled. Workflow is diverted from disabled functional components to enabled functional components.

Abstract: A method for communication over an SMB, I2C bus, or other serial bus between an auxiliary display subsystem and a secondary processor of a notebook including the auxiliary display subsystem, and systems, circuits and notebooks configured to perform the method. Typically, communication over the serial bus between the auxiliary display subsystem and secondary processor can occur when the notebook is in a standby or other low-power state (e.g., to obtain system status data or cause the notebook to wake up) or a fully-powered normal operating state. Typically, the auxiliary display subsystem is coupled not only to the notebook's secondary processor by the serial bus but also to the notebook's central processing unit by another link (e.g., a USB).