Abstract: A method for performing index compression. The method includes identifying a tile in an image, wherein the image comprises a plurality of tiles, wherein each tile includes color associated with a plurality of pixels. Furthermore, the method includes generating a plurality of indices located throughout the tile, and storing the plurality of indices. Additionally, the method includes offsetting zero or more locations of an index of the plurality of indices from a pixel location.

Abstract: A method for rendering paths. The method includes accessing data comprising a path, stenciling the path, wherein a bounding region of a plurality of stencil samples updated during the stenciling is accumulated, and provoking GPU hardware to produce a rasterized region for covering the bounding region as one object without interior edges.

Abstract: A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

Abstract: Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.

Abstract: Embodiments of the present invention are directed to methods and systems for performing automatic lens shading correction using module-specific calibrations. According to one aspect of the invention, a method is provided that is performed over three main stages. During a first stage, radial symmetric component data is determined that is common to camera modules of the type to be calibrated. During the second stage, the actual measurement of the shading profile of one or more specific camera modules is performed. In the third and final stage is the extrapolation stage, the base measurement surfaces of a camera module type determined in the first stage are extrapolated and modified with the module-specific Bezier correction surface and calibration data of the second stage. The output surfaces of this third and final stage are used to correct for the shading profile in the camera module, depending on the light-source estimation.

Abstract: A power supply system. The power system includes a power supply controller for supplying a control signal. The power system also includes a plurality of MOSFET drivers controlled by the control signal. The power system also includes a plurality of power channels. Each of the power channels includes a plurality of MOSFETs that is controlled by a corresponding MOSFET driver. The plurality of power channels is configured to generate a plurality of power signals, wherein the control signal controls delivery of the plurality of power signals through each of the power channels.

Abstract: Presented systems and methods can facilitate efficient voltage sensing and regulation. In one embodiment, a presented multiple point voltage sensing system includes Multiple point voltage sensing. Multi-point sensing is the scheme where voltage feedback from Silicon to the voltage regulator is an average from multiple points on the die. In one embodiment, multi-point sensing is done by placing multiple sense points across the partition/silicon and merging the sense traces from each sense point with balanced routing. In one embodiment, a presented multiple point voltage sensing system includes Virtual VDD Sensing with guaranteed non-floating feedback. In one exemplary implementation, Virtual VDD Sensing with guaranteed non-floating feedback allows more accurate sensing when a component is power gated off by removing the sensing results associated with the component.

Abstract: Data transfer techniques include transferring display surface data from a memory subsystem into a stutter buffer at a first rate until the stutter buffer is substantially full. The memory interface and/or memory of the memory subsystem may then be placed into a suspend state until the stutter buffer is substantially empty. The display surface data is transferred from the stutter buffer to display logic, at a second rate even when the memory subsystem is in a suspend state. The second rate, which is typically the rendering rate of the display, is substantially slower than the rate at which data is transferred into the stutter buffer.

Abstract: A method, in one embodiment, can include performing difference transformation of image samples. In addition, the method can also include performing length selection. The method can also include performing a prioritized ordering of difference data. Furthermore, the method can include performing packing that includes utilizing varying sized bit fields to produce a lossy compressed representation.

Abstract: Methods are provided to perform area summation of various subsections of data values in a regular input array of one or several dimensions and varying sizes. The summation is achieved by adding up values from a ripmap of partial sums, where the partial sums are computed from the input array using a binary reduction method. According to such embodiments, the generation of the ripmap of partial sums will employ several binary reduction stages. Within each stage, a reduction operator is used that adds two elements along the respective direction. This is repeated until the output is only one element wide in the respective direction. The addresses of partial sums in the ripmap may subsequently be computed using a binary analysis of the target subsections in order to choose those partial sum values for a desired area that results in the desired area sum using an optimal number of data fetches.

Abstract: A method for correcting a shift error in a fused multiply add operation. The method comprises adjusting a normalized floating-point number before performing a shift error correction to produce an adjusted normalized floating-point number, and correcting a shift error in the adjusted normalized floating-point number. The correcting the shift error comprises shifting a mantissa of the adjusted normalized floating-point number in one direction. A fused multiply add module comprising a normalizer module, a compensation logic, and a round. The normalizer module is operable to normalize a floating-point number to produce a normalized floating-point number. The floating-point number is normalized based upon an estimated quantity of leading zeros. The compensation logic is operable to manage a correction of a shift error in the normalized floating-point number. The rounder is operable to correct the shift error with a mantissa shift in only one direction.

Abstract: One embodiment provides a method for reducing leakage current in device logic having an operational supply-voltage threshold, a nonzero data-retention supply-voltage threshold, and two or more on-die transistor switches to switchably connect a voltage source to the device logic. After the logic enters an idle period, one or more of the switches are opened to lower a supply voltage of the logic below the operational supply-voltage threshold but above the data-retention supply-voltage threshold. When the logic exits the idle period, one or more of the switches are closed to raise the supply voltage of the logic above the operational supply-voltage threshold.

Abstract: A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming multiprocessor refuses the request. Otherwise, the streaming multiprocessor asserts the address lock, asserts a thread group lock in a plurality of thread group locks, where the thread group lock is associated with the thread group, and grants the request. One advantage of the disclosed techniques is that acquired locks are released when a thread is preempted. As a result, a preempted thread that has previously acquired a lock does not retain the lock indefinitely.

Abstract: A system and method for debugging an executing program. The method includes executing a general-purpose computing on graphics processing units (GPGPU) program. The GPGPU program comprises a first portion operable to execute on a central processing unit (CPU) and a second portion operable to execute on a graphics processing unit (GPU). The method further includes attaching a debugging program to the first portion of the GPGPU program and modifying the first portion of the GPGPU program. The attaching of the debugging program to the first portion of the GPGPU program pauses execution of the first portion of the GPGPU program. The method further includes resuming execution of the first portion of the GPGPU program and accessing a first state information corresponding to the first portion of the GPGPU program. Execution of the first portion of the GPGPU program may then be paused.

Abstract: Embodiments of the invention may include an apparatus that may include a graphics processor operable to generate video frames. Further, a screen refresh controller may be communicatively coupled with the graphics processor, wherein the screen refresh controller is operable to receive generated video frames from the graphics processor and send framelock signals to the graphics processor. In addition, a display device may be communicatively coupled with the screen refresh controller, wherein the display device is operable to receive and display video frames from the screen refresh controller.

Abstract: A system, method, and computer program product for applying a spatially varying unsharp mask noise reduction filter is disclosed. The spatially varying unsharp mask noise reduction filter generates a low-pass filtered image by applying a low-pass filter to a digital image, generates a high-pass filtered image of the digital image, and generates an unsharp masked image based on the low-pass filtered image and the high-pass filtered image. The filter also blends the low-pass filtered image with the unsharp masked image based on a shaping function.

Abstract: Novel solutions are provided for consistent Quality of Service in cloud gaming system that adaptively and dynamically compensate for poor network conditions by moderating rendered frame rates using frame rate capping to optimize for network latency savings (or surplus). In further embodiments, the encoding/sent frame rate to the client can also be managed in addition, or as an alternative to capping the rendered frame rates. The claimed embodiments not only maintain a constant Quality of Service (QoS) for the user, but may also be employed to leverage higher-performing networks to reduce operational costs.

Abstract: Technology is provided for distributed power delivery to a processing unit on a printed circuit board. In one example, a printed circuit board includes a processing unit coupled to multiple power channels, including first channels on a first side of the processing unit, and second channels on a second side of the processing unit. The printed circuit board further includes a first power supply coupled to the processing unit via the first channels, and a second power supply coupled to the processing unit via the second channels. The processing unit is configured to receive a total current, including currents drawn substantially simultaneously from the first power supply and the second power supply. The total current is about equivalent to a current the processing unit would draw from a single power supply.

Abstract: A cloud gaming system includes a cloud gaming server that provides rendering for a video frame employed in cloud gaming. The cloud gaming system also includes a video frame latency reduction pipeline coupled to the cloud gaming server, having a slice generator that provides a set of separately-rendered video frame slices required for a video frame, a slice encoder that encodes each of the set of separately-rendered video frame slices into corresponding separately-encoded video frame slices of the video frame and a slice packetizer that packages each separately-encoded video frame slice into slice transmission packets. The cloud gaming system further includes a cloud network that transmits the slice transmission packets and a cloud gaming client that processes the slice transmission packets to construct the video frame. A video frame latency reduction method is also provided.

Abstract: A method, in one embodiment, can include performing difference transformation of image samples. In addition, the method can also include performing length selection. Furthermore; the method can include performing packing that includes utilizing varying sized bit fields to produce a compressed representation.