Patents Assigned to NVidia
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Publication number: 20140176529Abstract: A tile shader for screen space of a graphics pipeline, a method of rendering graphics and a graphics processing unit are disclosed. In one embodiment, the tile shader includes: (1) an input interface configured to receive a tile of pixels for processing and (2) a tile processor configured to perform tile-level processing of the pixels.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: NvidiaInventor: Albert Meixner
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Publication number: 20140181339Abstract: A method comprises selecting a starting point on a map of equalization coefficients and measuring an eye height of a signal transmitted using the set of equalization coefficients associated with the starting point and an eye height associated with each adjacent point on the map relative to the starting point. The eye height associated with an adjacent point is based on a signal transmitted using the set of equalization coefficients associated with the adjacent point. The method also comprises walking on the map in a first direction from the starting point to the adjacent point associated with the greatest eye height, wherein the eye height associated with the adjacent point is greater than or equal to the eye height associated with the starting point.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Michael Hopgood, Robert Huang, Vishal Mehta, Hitendra Dutt
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Publication number: 20140175619Abstract: An integrated circuit system includes an interposer substrate with an electrical reference plane, or “ground plane,” formed by a conductive semiconductor layer. The conductive semiconductor layer may be formed in a surface region of the interposer substrate, and in some embodiments is formed by performing an ion implant process on the surface region to increase the electrical conductivity of the surface region. Because the surface region is electrically coupled to an electrical ground of the integrated circuit system, the surface region functions as a ground plane that helps contain electric fields produced by signals routed through interconnects of the interposer substrate. Consequently, a ground plane can be formed on a surface of the interposer substrate without forming a metalization layer.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Abraham F. Yee, Mayan Riat
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Publication number: 20140176545Abstract: A system, method, and computer program product for implementing an algorithm for performing thin voxelization is disclosed. The thin voxelization algorithm receives a surface, maps the surface onto a plurality of volumetric picture elements (voxels), and generates a value for each voxel in the plurality of voxels that intersects with the surface.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventor: Samuli Matias Laine
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Publication number: 20140176569Abstract: Employing a general processing unit as a programmable function unit of a graphics pipeline and a method of manufacturing a graphics processing unit are disclosed. In one embodiment, the graphics pipeline includes: (1) accelerators, (2) an input output interface coupled to each of the accelerators and (3) a general processing unit coupled to the input output interface and configured as a programmable function unit of the graphics pipeline, the general processing unit configured to issue vector instructions via the input output interface to vector data paths for the programmable function unit.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventor: Albert Meixner
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Publication number: 20140181547Abstract: A hybrid battery pack and a power supply procedure for supplying power to a mobile computing system comprising a Li polymer battery coupled in parallel with a supercapacitor cell battery. The Li polymer battery supplies substantially all the continuous currents demanded by the system load. The supercapacitor cell battery supplies substantially all the transient current demanded by the system load. A charging control logic circuit is coupled to the power source and the system load, and operable to control the Li polymer battery to charge the supercapacitor cell battery at a constant rate while the supercapacitor cell battery supplies current to the system load. The control logic can also send instructions to have system load reduced if the supercapacitor cell battery is depleted before it can be charged with an external charger.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventor: Jevons Hua
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Publication number: 20140181452Abstract: A method of training command signals for a memory module. The method includes programming a memory controller into a mode wherein a column access strobe is active for a single clock cycle. The method then programs a programmable delay line of the column access strobe with a delay value and performs initialization of the memory module. A read command is then sent to the memory module. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.Type: ApplicationFiled: December 27, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
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Publication number: 20140176116Abstract: A first instance and a second instance of an oscillating circuit are each formed as part of an integrated circuit and are used to monitor degradation over time of one or more portions of the integrated circuit. The first instance of the oscillating circuit is configured to be coupled to a power source during normal operation of the integrated circuit and the second instance is configured to be decoupled from the power source. Over the lifetime of the integrated circuit, the first instance undergoes degradation from use while the second instance of the oscillating circuit remains unpowered, therefore experiencing essentially no use-related degradation. During a testing operation, the second instance can be used as a reference circuit that accurately quantifies use-related degradation of the first instance of the oscillating circuit and, by extension, one or more portions of the integrated circuit.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Hemant KUMAR, Matthew Raymond LONGNECKER, Brian SMITH
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Publication number: 20140176575Abstract: A system, method, and computer program product are provided for tiled deferred shading. In operation, a plurality of photons associated with at least one scene are identified. Further, a plurality of screen-space tiles associated with the at least one scene are identified. Additionally, each of the plurality of screen-space tiles capable of being affected by a projection of an effect sphere for each of the plurality of photons are identified. Furthermore, at least a subset of photons associated with each of the screen-space tiles from which to compute shading are selected. Moreover, shading for the at least one scene is computed utilizing the selected at least a subset of photons.Type: ApplicationFiled: August 30, 2013Publication date: June 26, 2014Applicant: NVIDIA CorporationInventors: Morgan McGuire, Michael Thomas Mara, David Patrick Luebke, Jacopo Pantaleoni
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Publication number: 20140176745Abstract: An approach is provided for a user interface for enabling control of a camera. In one example, a method includes the following: displaying a tone mapped high dynamic range (HDR) image on a user interface device of the camera; receiving user edits via an input device associated with the user interface device; sending the user edits to one or more back-end devices of the camera to perform processing operations based on the user edits; receiving an updated tone mapped HDR image from the one or more back-end devices, wherein the updated tone mapped HDR image is generated from the processing operations performed based on the user edits; and displaying the updated tone mapped HDR image on the user interface as the camera lens continues to capture frames of the scene for the one or more back-end devices to perform operations that iteratively affect the updated tone mapped HDR image.Type: ApplicationFiled: March 1, 2013Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Dawid Stanislaw PAJAK, Jongmin BAEK, Kari PULLI
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Publication number: 20140176588Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Jerome F. Duluk, JR., Ziyad S. Hakura, Henry Packard MORETON
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Publication number: 20140176041Abstract: A system and method for recycling the electrical energy that has been consumed and converted into unwanted thermal energy. A power source for supplying power to a mobile computing system comprises a rechargeable battery and a semiconductor thermoelectric module coupled to the rechargeable battery and a charring circuit. The thermoelectric module is disposed proximate to a heat generating member of the computing system and operable to sense the thermal energy released by the member and convert it into electrical energy based on Seeback effect. The converted electrical energy can be regulated and stored in the rechargeable battery.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventor: Xiang Sun
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Publication number: 20140181540Abstract: A power source for supplying power to a mobile computing system comprising a Li polymer battery coupled in parallel with a supercapacitor cell battery. The Li polymer battery supplies substantially all the continuous currents demanded by the system load. The supercapacitor cell battery supplies substantially all the transient current demanded by the system load. The Li polymer battery may charge the supercapacitor cell battery when the voltage difference is larger than the difference caused by internal impedance difference.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventor: NVIDIA CORPORATION
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Publication number: 20140177695Abstract: A method comprises performing a first pass test over a plurality of sets of equalization coefficients to filter the plurality of sets of equalization coefficients to produce one or more filtered sets of equalization coefficients. Each filtered set of equalization coefficients meets a first predetermined threshold. The method also comprises performing a second pass test over the one or more filtered sets of equalization coefficients to determine a final set of equalization coefficients that meets a second predetermined threshold. The second pass test produces more accurate results than the first pass test.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Hungse Cha, Robert Huang, Vishal Mehta, Feroze Karim, Dennis Kd Ma, Michael Hopgood, Srikanth Devarapalli
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Patent number: 8760535Abstract: In an embodiment, computational complexity of estimating the actual illuminant of a scene is reduced by examining only a subset of the pixel values generated for a received image frame. In another embodiment, number of rotations of color values is minimized by selecting an area which contains the color cue values of a color in an original/unrotated coordinate space and has boundaries which parallel the axis of the original coordinate space, and rotating a color value only if the color value is within the selected area. In another embodiment, such an area is used in conjunction with a histogram-based approach to determine the actual illuminant.Type: GrantFiled: December 31, 2009Date of Patent: June 24, 2014Assignee: Nvidia CorporationInventor: Anurag Goel
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Patent number: 8761046Abstract: A modem is disclosed that, in one embodiment, includes: first interface apparatus comprising a first wireless transceiver arranged to connect to a wireless cellular network; second interface apparatus arranged to connect to the terminal; and processing apparatus configured as a wireless cellular modem for accessing packet-based communications. The processing apparatus is arranged to receive at least one first address from the wireless cellular network via the first interface apparatus, the first address being an address of a server of a name-to-address resolution system.Type: GrantFiled: December 8, 2011Date of Patent: June 24, 2014Assignee: Nvidia CorporationInventors: Flavien Delorme, Bruno De Smet, Farouk Belghoul
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Patent number: 8761253Abstract: The following embodiments describe an approach for selecting an intra prediction mode for video encoding, such as occurs in the H.264 standard. One embodiment describes a method of selecting an optimum intra prediction mode. This method involves selecting a first intra prediction mode, which is used to determine a search order for a number of intra prediction modes. These intra prediction modes are then evaluated in order to identify the optimum intra prediction mode.Type: GrantFiled: May 28, 2008Date of Patent: June 24, 2014Assignee: NVIDIA CorporationInventors: Atul Garg, Thomas Karpati, Jackson Lee, Ignatius Tjandrasuwita
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Patent number: 8762759Abstract: To reduce power consumption, a processor can be placed into a reduced power state. Before doing so, interrupt events can be designated as wakeup events. While the processor is in the reduced power state, if an event designated as a wakeup event occurs, then a signal is directed to a wakeup event handler instead of to an interrupt handler. In response to the signal, the wakeup event handler causes power to be restored to the processor, so that the event can be subsequently serviced.Type: GrantFiled: April 10, 2008Date of Patent: June 24, 2014Assignee: Nvidia CorporationInventors: Scott Alan Williams, Aleksandr Frid, Udaykumar Raval, Shailendra Chafekar
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Patent number: 8762214Abstract: A method for hierarchical product selection and purchasing from a server. The method includes accessing a plurality of products from a plurality of component subareas, wherein the products are for an assembly of a computer system, and wherein each of the component subareas have corresponding compatibility constraints with respect to other component subareas. A hierarchical presentation of the products is generated, wherein the presentation proceeds from a parent product out of the plurality of products to a child product out of the plurality of products. The hierarchical presentation of the products are provided to a client computer system via a Web browser hosted on the client computer system, wherein the presentation is configured to show child component subareas that satisfy compatibility restraints with parent component subareas. An order for the at least one product is accepted and implemented with a corresponding e-commerce agent for the product.Type: GrantFiled: November 14, 2006Date of Patent: June 24, 2014Assignee: Nvidia CorporationInventors: Christopher J. Daniel, Norbert A. Kordsmeier, Randolph S. Reynolds, IV, Elizabeth H. Austin, Eric Henze
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Patent number: 8760204Abstract: A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.Type: GrantFiled: November 20, 2012Date of Patent: June 24, 2014Assignee: NVIDIA CorporationInventors: William J. Dally, Stephen G. Tell