Abstract: A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.

Abstract: In a deblocking operation, pixel values within a first block of pixels are compared, and pixel values in the first block are also compared to pixel values in a second block of pixels that is adjacent to the first block. Based on the results of the comparisons, a digital deblocking filter and a region of interest can be selected, where the region of interest identifies a number of pixels in the first block and a number of pixels in the second block to which the selected filter is to be applied.

Abstract: One embodiment of the present invention sets forth a technique for using a shared memory to store hardware-managed virtual buffers. A circular buffer is allocated within a general-purpose multi-use cache for storage of primitive attribute data rather than having a dedicated buffer for the storage of the primitive attribute data. The general-purpose multi-use cache is also configured to store other graphics data sinces the space requirement for primitive attribute data storage is highly variable, depending on the number of attributes and the size of primitives. Entries in the circular buffer are allocated as needed and released and invalidated after the primitive attribute data has been consumed. An address to the circular buffer entry is transmitted along with primitive descriptors from object-space processing to the distributed processing in screen-space.

Abstract: One embodiment of the present invention sets forth a technique for reducing overhead associated with transmitting primitive draw commands from memory to a graphics processing unit (GPU). Command pairs comprising an end draw command and a begin draw command associated with a conventional graphics application programming interface (API) are selectively replaced with a new construct. The new construct is a reset topology index, which implements a combined function of the end draw command and begin draw command. The new construct improves efficiency by reducing total data transmitted from memory to the GPU.

Abstract: In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify an arithmetic operation specified in the instruction, and execution logic configured to receive operands specified by the instruction. The execution logic includes a primary logic path configured to perform the arithmetic operation on such operands and a secondary parallel logic path configured to output metadata associated with the result of the arithmetic operation.

Abstract: An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.

Abstract: An integrated circuit system includes a heat spreader that is thermally coupled to a semiconductor chip and has a cavity or opening formed in the heat spreader. The cavity or opening is positioned so that capacitors and/or other passive components mounted to the same packaging substrate as the semiconductor chip are at least partially disposed in the cavity or opening. Because the passive components are disposed in the cavity or opening, the integrated circuit system has a reduced package thickness.

Abstract: One embodiment sets forth a method for processing draw calls that includes setting up a plurality of shader input buffers in memory, receiving shader input data related to a graphics scene from a software application, storing the shader input data in the plurality of shader input buffers, computing a pointer to each shader input buffer included in the plurality of shader input buffers, and passing the pointers to the plurality of shader input buffers to the software application. By implementing the disclosed techniques, a shader program advantageously can access the shader input data associated with a graphics scene and stored in various shader input buffers without having to go through the central processing unit to have the shader input buffers binded to the shader program.

Abstract: In embodiments of the invention, an apparatus may include a display comprising a plurality of pixels and a computer system coupled with the display and operable to instruct the display to display images. The apparatus may further include a microlens array located adjacent to the display and comprising a plurality of microlenses, wherein the microlens array is operable to produce a light field by altering light emitted by the display to simulate an object that is in focus to an observer while the display and the microlens array are located within a near-eye range of the observer.

Abstract: An external latching mechanism for an Input/Output (I/O) connection between devices is provided. In one embodiment, an external latching mechanism for an Input/Output (I/O) cable is provided. The external latching mechanism includes a housing coupled to an I/O cable at a first end and having an I/O connector extending a second end. An external latch is coupled by a mounting portion to the housing. The external latch has a first end and a second end. The second end of the arm extends beyond the second end of the housing to a barb. In another embodiment, an external latching Input/Output (I/O) connection is provided that includes a I/O card latching bracket configured to mate with an I/O cable assembly.

Abstract: A system and method for launching data parallel and task parallel application threads. In one embodiment, the system includes: (1) a global thread launcher operable to retrieve a launch request from a queue and track buffer resources associated with the launch request and allocate output buffers therefor and (2) a local thread launcher associated with a streaming multiprocessor and operable to receive the launch request from the global thread launcher, set a program counter and resource pointers of pipelines of the streaming multiprocessor and receive reports from pipelines thereof as threads complete execution.

Abstract: One embodiment of the present invention sets forth a method for analyzing the performance of a graphics processing pipeline. A first workload and a second workload are combined together in a pipeline to generate a combined workload. The first workload is associated with a first instance and the second workload is associated with a second instance. A first and second initial event are generated for the combined workload, indicating that the first and second workloads have begun processing at a first position in the graphics processing pipeline. A first and second final event are generated, indicating that the first and second workloads have finished processing at a second position in the graphics processing pipeline.

Abstract: Embodiments of the invention generally include apparatus for providing a positive locked connection for I/O devices to computing devices. In one embodiment, an external latching apparatus for an Input/Output (I/O) connection is provided. The external latching apparatus includes a main body and at least one latch. The main body includes a first surface configured to abut to an I/O card bracket and a second surface, parallel and spaced apart from the first surface. The at least one latch extends from the main body beyond the first surface. A plurality of parallel slots are formed in the second surface. Each slot is open on a bottom side of the body and is configured to receive a cable of an I/O cable assembly.

Abstract: A message handler, a method of handling message delivery and a message delivery device. In one embodiment, the message handler includes: (1) a network interface operable to detect a receipt of an inbound message via a communication network and (2) an alert manager associated with the network interface and operable to employ calendar data of a user to make a determination of whether a message delivery device associated with the user should generate an alert to the user regarding the receipt.

Abstract: A passive cooling system is provided for dissipating heat from an electronic component. The system includes a printed circuit board including a first dielectric layer and a first conductive layer, an electronic component coupled to the printed circuit board via a plurality of electrical contacts, and a cooling component thermally coupled to the electronic component through the first conductive layer by a micro via thermal array.

Abstract: A system and method are provided for connecting a system on chip (SoC) processor and an external processor. The SoC processor receives as input a content stream, and processes the content stream. Further, the application processor that is connected to the SoC processor receives the processed content stream, performs further processing on the processed content stream, and outputs the further processed content stream hack to the SoC processor.

Abstract: A system and method are provided for display of a 3D image on a video monitor. A characteristic of each of a plurality of sample LCD panels is measured and a display parameter is calculated based on the measured characteristics. A first 3D image is displayed on one of the sample LCD panels using the calculated display parameter and the displayed image is evaluated. Based on the evaluation, each of the sample LCD panels is assigned to one of a plurality of groups. For each group, a group display parameter is calculated based on the measured characteristics of the panels assigned to the group. A video monitor controller is configured to display a second 3D image on an installation LCD panel. The second 3D image is displayed based on the group display parameters and an indication of a group to which the installation LCD panel is assigned.

Abstract: A method is provided for depicting on a display, an object within a simulated environment having clothing. In this method, the clothing is represented as a series of vertices that include vertices that are attached to the object and vertices that are not attached to the object. The method improves upon position based dynamics algorithm by constraining unattached vertices to be a predefined distance away from attached vertices that are connected thereto to compensate for overstretching in the simulated clothing.

Abstract: Techniques are disclosed for tracing a ray within a parallel processing unit. A first thread receives a ray or a ray segment for tracing and identifies a first node within an acceleration structure associated with the ray, where the first node is associated with a volume of space traversed by the ray. The thread identifies the child nodes of the first node, where each child node is associated with a different sub-volume of space, and each sub-volume is associated with a corresponding ray segment. The thread determines that two or more nodes are associated with sub-volumes of space that intersect the ray segment. The thread selects one of these nodes for processing by the first thread and another for processing by a second thread. One advantage of the disclosed technique is that the threads in a thread group perform ray tracing more efficiently in that idle time is reduced.

Abstract: One embodiment of the invention sets forth a method that includes receiving a request from a client device to launch an application program for execution on a server device, where the application program is configured to operate in a full-screen display mode, and, in response, creating an execution environment for the application program that disables the full-screen display mode. Within the execution environment, the application program is configured to generate the rendered image data for display on the client device. With the disclosed approach, application programs that are configured to execute on an application server computer system in a full-screen display mode can be executed through an execution environment that includes a shim layer configured to disable the full-screen display mode and transmit the render image data to a client device for display.