Patents Assigned to NVidia
  • SYSTEM AND METHOD FOR VERSIONING BUFFER STATES AND GRAPHICS PROCESSING UNIT INCORPORATING THE SAME
    Publication number: 20140168227
    Abstract: A system and method for versioning states of a buffer. In one embodiment, the system includes: (1) a page table lookup and coalesce circuit operable to provide a page table directory request for a translatable virtual address of the buffer to a page table stored in a virtual address space and (2) a page directory processing circuit associated with the page table lookup and coalesce circuit and operable to provide a translated virtual address based on the virtual address and a page table load response received from the page table.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Albert Meixner
  • FINE-GRAINED PARALLEL TRAVERSAL FOR RAY TRACING
    Publication number: 20140168228
    Abstract: Techniques are disclosed for tracing a ray within a parallel processing unit. A first thread receives a ray or a ray segment for tracing and identifies a first node within an acceleration structure associated with the ray, where the first node is associated with a volume of space traversed by the ray. The thread identifies the child nodes of the first node, where each child node is associated with a different sub-volume of space, and each sub-volume is associated with a corresponding ray segment. The thread determines that two or more nodes are associated with sub-volumes of space that intersect the ray segment. The thread selects one of these nodes for processing by the first thread and another for processing by a second thread. One advantage of the disclosed technique is that the threads in a thread group perform ray tracing more efficiently in that idle time is reduced.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA Corporation
    Inventors: David LUEBKE, Timo AILA, Jacopo PANTALEONI, David TARJAN
  • TECHNIQUE FOR ACCESSING CONTENT-ADDRESSABLE MEMORY
    Publication number: 20140173193
    Abstract: A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Brian Fahs, Eric T. ANDERSON, Nick Barrow-Williams, Shirish GADRE, Joel James MCCORMACK, Bryon S. NORDQUIST, Nirmal Raj Saxena, Lacky V. Shah
  • STEREO VIEWPOINT GRAPHICS PROCESSING SUBSYSTEM AND METHOD OF SHARING GEOMETRY DATA BETWEEN STEREO IMAGES IN SCREEN-SPACED PROCESSING
    Publication number: 20140168232
    Abstract: A stereo viewpoint graphics processing subsystem and a method of sharing geometry data between stereo images in screen-space processing. One embodiment of the stereo viewpoint graphics processing subsystem configured to render a scene includes: (1) stereo frame buffers configured to contain respective pixel-wise rendered scene data for stereo images, and (2) a sharing decision circuit operable to determine when to share geometric data between the stereo frame buffers for carrying out screen-space effect processes to render the scene in the stereo images.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: G. Evan Hart, Cem Cebenoyan, Louis Bavoil
  • ASYNCHRONOUS COMPUTE INTEGRATED INTO LARGE-SCALE DATA RENDERING USING DEDICATED, SEPARATE COMPUTING AND RENDERING CLUSTERS
    Publication number: 20140168230
    Abstract: An asynchronous computing and rendering system includes a data storage unit that provides storage for processing a large-scale data set organized in accordance to data subregions and a computing cluster containing a parallel plurality of asynchronous computing machines that provide compute results based on the data subregions. The asynchronous computing and rendering system also includes a rendering cluster containing a parallel multiplicity of asynchronous rendering machines coupled to the asynchronous computing machines, wherein each rendering machine renders a subset of the data subregions. Additionally, the asynchronous computing and rendering system includes a data interpretation platform coupled to the asynchronous rendering machines that provides user interaction and rendered viewing capabilities for the large-scale data set. An asynchronous computing and rendering method is also provided.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Marc Nienhaus, Joerg Mensmann, Hitoshi Yamauchi
  • NEAR-EYE PARALLAX BARRIER DISPLAYS
    Publication number: 20140168034
    Abstract: In embodiments of the invention, an apparatus may include a display comprising a plurality of pixels and a computer system coupled with the display and operable to instruct the display to display images. The apparatus may further include an SLM array located adjacent to the display and comprising a plurality of SLMs, wherein the SLM array is operable to produce a light field by altering light emitted by the display to simulate an object that is in focus to an observer while the display and the SLM array are located within a near-eye range of the observer.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: David Patrick Luebke, Douglas Lanman, Thomas F. Fox, Gerrit Slavenburg
  • NEAR-EYE OPTICAL DECONVOLUTION DISPLAYS
    Publication number: 20140168035
    Abstract: In embodiments of the invention, an apparatus may include a display comprising a plurality of pixels. The apparatus may further include a computer system coupled with the display and operable to instruct the display to display a deconvolved image corresponding to a target image, wherein when the display displays the deconvolved image while located within a near-eye range of an observer, the target image may be perceived in focus by the observer.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA Corporation
    Inventors: David Patrick Luebke, Douglas Lanman, Thomas F. Fox, Gerrit Slavenburg
  • TECHNIQUE FOR PERFORMING MEMORY ACCESS OPERATIONS VIA TEXTURE HARDWARE
    Publication number: 20140173258
    Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Brian FAHS, Eric T. ANDERSON, Nick BARROW-WILLIAMS, Shirish GADRE, Joel James MCCORMACK, Bryon S. NORDQUIST, Nirmal Raj SAXENA, Lacky V. SHAH
  • METHOD AND SYSTEM OF EMULATING PRESSURE SENSITIVITY ON A SURFACE
    Publication number: 20140168093
    Abstract: A system and method for emulating pressure-sensitivity are presented. Embodiments of the present invention provide a novel solution to generate emulated pressure data in response to contact made with a touch sensitive device, in that embodiments of the present invention expose more information about the contact in the form of location information of the contact, surface area data associated with the contact at the time contact was made, as well as a surface area data and calculated rates of change between the surface areas touched over time. In response to the input received, an emulated pressure computation module may then produce emulated pressure data which may be received by applications operable to utilize pressure input through an application programming interface coupling these applications to the emulation pressure computation module.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Philip Lawrence
  • STREAMING PROCESSING OF SHORT READ ALIGNMENT ALGORITHMS
    Publication number: 20140173606
    Abstract: A technique for executing alignment algorithms on a SIMT processing environment is disclosed. An alignment algorithm having multiple stages is executed within the SIMT environment such that a different thread group executes each stage of the algorithm. Each thread group performs a different set of alignment operations related to a different stage of alignment algorithm for a group of short reads. In such a manner, the thread groups operate in unison to perform all the operations related to each stage of the alignment algorithm on every short read in the group of short reads.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA Corporation
    Inventor: Jacopo PANTALEONI
  • MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES
    Publication number: 20140169108
    Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ge Yang, Hwong-Kwo Lin, Xi Zhang, Jiani Yu, Haiyan Gong
  • APPARATUS AND METHOD FOR ENHANCING MOTION ESTIMATION BASED ON USER INPUT
    Publication number: 20140169471
    Abstract: A method and apparatus for enhancing motion estimation based on user input are provided. The motion estimation apparatus used for video encoding comprises a receiver operable to receive a user based input and an input analysis module operable to analyzed the user based input. The apparatus also comprises an encoder that is operable to compute displacement coordinates from the analyzed user based input for a current block in a target frame of a video stream and operable to determine a search area in a reference frame to search for a best match for the current block using the displacement coordinates. The encoder can also comprise a block match module operable to find a best match block for the current block in the search area of the reference frame using a block matching procedure.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Helix He
  • TECHNIQUE FOR PERFORMING MEMORY ACCESS OPERATIONS VIA TEXTURE HARDWARE
    Publication number: 20140168245
    Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Brian Fahs, Eric T. Anderson, Nick Barrow-Williams, Shirish Gadre, Joel James McCormack, Bryon S. Nordquist, Nirmal Raj Saxena, Lacky V. Shah
  • OPTIMIZING TRIANGLE TOPOLOGY FOR PATH RENDERING
    Publication number: 20140168222
    Abstract: A technique for efficiently rendering path images tessellates path contours into triangle tans comprising a set of representative triangles. Topology of the set of representative triangles is then optimized for greater rasterization efficiency by applying a flip operator to selected triangle pairs within the set of representative triangles. The optimized triangle pairs are then rendered using a path rendering technique, such as stencil and cover.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jeffrey A. Bolz, Mark J. Kilgard
  • TECHNIQUE FOR SIMULATING THE DYNAMICS OF HAIR
    Publication number: 20140172380
    Abstract: A simulation engine is configured to generate a physical simulation of a chain of particles by implementing a physics-based algorithm. The simulation engine is configured to generate a predicted position for each particle and to then adjust the predicted position of each particle based on a set of constraints associated with the physics-based algorithm. The simulation engine may then generate a predicted velocity for a given particle based on the adjusted, predicted position of that particle and based on the adjusted, predicted position of an adjacent particle.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Matthias Muller-Fischer, Nuttapong CHENTANEZ, Tae-Yong KIM
  • APPROACH FOR WORKING AROUND STARVATION PROBLEMS IN A DATAPATH
    Publication number: 20140173148
    Abstract: A starvation control engine operable to monitor data transactions within a computer system potentially prevents or corrects starvation issues. The starvation control engine is programmed to generate one or more bubbles in a data path based on one or more trigger events. The trigger events or the criteria underlying the trigger events may be programmed or changed by at least one of a user or the starvation control engine. The starvation control engine determines when, for how long, and how often to generate the one or more bubbles based on the type of event.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Dennis Kd Ma, Utpal Barman
  • SMALL AREA LOW POWER DATA RETENTION FLOP
    Publication number: 20140167828
    Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ge Yang, Hwong-Kwo Lin, Xi Zhang, Jiani Yu
  • Efficient encoding/decoding of a sequence of data frames
    Patent number: 8756482
    Abstract: Encoding data by first performing a transformation of predicted data and input data, and then performing a subtraction of the resulting outputs. In an embodiment, the prediction approach is chosen such that fewer elements of different values (compared to a number of elements in the input data) are generated, and the different values are generated in a predictable position. The transformation approach is chosen such that the output expressly represents variations in the input data as well as satisfies a distributive property. The decoding may be performed based on the same concepts. As a result, the data can be encoded and/or decoded efficiently.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: June 17, 2014
    Assignee: NVIDIA Corporation
    Inventor: Anurag Goel
  • COMPUTING TESSELLATION COORDINATES USING DEDICATED HARDWARE
    Publication number: 20140160126
    Abstract: A system and method for performing tessellation of three-dimensional surface patches performs some tessellation operations using programmable processing units and other tessellation operations using fixed function units with limited precision. (u,v) parameter coordinates for each vertex are computed using fixed function units to offload programmable processing engines. The (u,v) computation is a symmetric operation and is based on integer coordinates of the vertex, tessellation level of detail values, and a spacing mode.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 12, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Justin S. LEGAKIS, Emmett M. KILGARIFF, Michael C. SHEBANOW
  • BRACKET OF ADD-IN CARD OF COMPUTER, ADD-IN CARD SYSTEM AND COMPUTER
    Publication number: 20140160662
    Abstract: A bracket of an add-in card of an electronic device is provided. The bracket, in one embodiment, includes a body in a shape of a sheet, wherein the body is provided with an opening, the opening configured to correspond to an interface adapter on the add-in card and expose an interface part of the interface adapter in an installed state when the bracket is installed to the add-in card. The bracket, in this embodiment, further includes a conductive component in electrical connection with the body, the conductive component configured to electrically connect with a housing of the interface adapter in the installed state, wherein at least a portion of the body is made of a conductive material so that the conductive component is electrically connected with a chassis via the body when installed.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 12, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Zhi Li, Qiang CHEN, Charlie J. Shu