Abstract: In an embodiment, computational complexity of estimating the actual illuminant of a scene is reduced by examining only a subset of the pixel values generated for a received image frame. In another embodiment, number of rotations of color values is minimized by selecting an area which contains the color cue values of a color in an original/unrotated coordinate space and has boundaries which parallel the axis of the original coordinate space, and rotating a color value only if the color value is within the selected area. In another embodiment, such an area is used in conjunction with a histogram-based approach to determine the actual illuminant.

Abstract: Metrics representing a combined measure of power used by a central processing unit (CPU) and power used by a graphics processing unit (GPU) are compared to a shared supply power and thermal power budgets. Power used by the CPU and power used by the GPU are regulated in tandem using a fuzzy logic control system that can implement fuzzy rules that describe the management within thermal and supply power design constraints of the platform.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.

Abstract: A system, method, and computer program product are provided for optimizing use of a vertex cache. In use, information is identified, where such information is associated with vertex data stored in a vertex cache. To this end, use of the vertex cache may be optimized utilizing the information. In one embodiment, the information may include new information derived from the vertex data, and optionally index data, prior to processing of the vertex data. Further, the vertex cache may optionally utilize the information to optimize performance of the vertex cache by minimizing a number of cache misses.

Abstract: One embodiment of the present invention sets forth technique for watertight tessellation in a displaced subdivision surface. A subdivision surface is represented as a novel parametric quad patch that is continuous with respect to position (C0) and partial derivatives (C1) along boundaries as well as interior regions. The novel parametric quad patch is referred to herein as a Hermite Gregory patch and comprises a Hermite patch augmented to include a pair of twist vector parameters per vertex. Each pair of twist vectors is combined into one twist vector during evaluation, according to weights based on proximity to parametric boundaries. Evaluation yields an approximation mesh comprising a position for each vertex and a corresponding normal vector for the vertex. Displacement is performed based on the approximation mesh and a displacement map to generate a displaced approximation mesh that is reflective of the displaced subdivision surface.

Abstract: A rolling shutter digital camera. Each photographic image of a given exposure duration is captured as a multi-frame burst of frames each having a shorter exposure duration to minimize motion blur and to reduce sensor noise by averaging. Each frame is quantized into swaths, captured sequentially by the rolling shutter. Swaths of the first frames are analyzed to select a set of best motion detection reference regions. Swaths of subsequent frames are analyzed versus only those regions, to reduce required computation, and are re-registered accordingly. Corresponding swaths of each frame are accumulated. The accumulator is normalized to the desired bit depth and written as the final image. Averaging of the multiple frames is improved by re-registering swaths rather than entire frames, because of the time delta caused by the rolling shutter.

Abstract: A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example, a memory stores information and instructions for the engines. The shared resource management unit manages memory operations and handles access requests associated with compressed data.

Abstract: A method and system for application development. Specifically, a generic console interface is provided that is capable of interacting with graphics applications. The console interface is capable of accessing a graphics application by detouring at least one predefined system call made by the graphics application. User input is intercepted that is related to the predefined system call that is detoured. The user input is communicated through the console interface. An operation is performed as implemented by the user input through a dynamically loadable module.

Abstract: One embodiment of the present invention sets forth a technique for rendering clipped paths by first generating clip stencil buffer state indicating pixels that are inside of the clip path. The clip stencil buffer state may also store an opacity value for each covered pixel to generate a mask that modulates the opacity of a draw path that is clipped. Clipped draw stencil buffer state is then generated indicating pixels of the draw path that should be covered based on the clip stencil buffer state and coverage of the draw path. The clipped draw path is then filled or stroked to produce the clipped draw path. The clip and draw paths may be filled or stroked without tessellating the paths. Path rendering may be accelerated when a GPU or other processor that is configured to perform operations to generate the clip stencil buffer state and the clipped draw stencil buffer state, and to fill or stroke the clipped draw path.

Abstract: A portable computer system is disclosed according to the invention. The portable computer system comprises: a multi-functional processing unit with power consumption of no more than approximately 10 watts consisting of a single chip having a plurality of processors thereon, wherein each processor is operable for at least one task selected from a group consisting of computing, graphic processing and audio processing; a mother board to which the multi-functional processing unit is connected; a memory unit connected to the motherboard and in communication with the multi-functional processing unit; and an I/O interface connected to the motherboard and in communication with the multi-functional processing unit, the portable computer system is configured to insert into a interface of a peripheral device to communicate between the portable computer system and the peripheral device.

Abstract: One embodiment of the present invention sets forth a technique for converting dashed strokes into quadratic Bèzier segment sequences. Path rendering with stroking and dashing may be accelerated when a graphics processing unit or other processor is configured to subdivide quadratic Bèzier segments based on the remaining distance for a current dash pattern element and the arc length of the current quadratic Bèzier path segment to generate “on” dash pattern segments. Each “on” dash pattern segment is then bounded by a conservative geometric hull. A point containment technique is then used to identify pixels within each conservative geometric hull that are within half of the stroke width of any point along a path to be stroked.

Abstract: A method for traversing pixels of an area is described. The method includes the steps of traversing a plurality of pixels of an image using a first boustrophedonic pattern along a predominant axis, and, during the traversal using the first boustrophedonic pattern, traversing a plurality of pixels of the image using a second boustrophedonic pattern. The second boustrophedonic pattern is nested within the first boustrophedonic pattern.

Abstract: A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.

Abstract: A method for thread address mapping in a parallel thread processor. The method includes receiving a thread address associated with a first thread in a thread group; computing an effective address based on a location of the thread address within a local window of a thread address space; computing a thread group address in an address space associated with the thread group based on the effective address and a thread identifier associated with a first thread; and computing a virtual address associated with the first thread based on the thread group address and a thread group identifier, where the virtual address is used to access a location in a memory associated with the thread address to load or store data.

Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.

Abstract: A system, method, and computer program product are provided for performing level shifting. In use, level shifting is performed utilizing a native transistor, where the level shifting is performed utilizing a feedback based topology.

Abstract: An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.

Abstract: An 8-transistor SRAM (static random access memory) storage cell provides differential read bit lines that are precharged to a low voltage level for read operations. The 8-transistor storage cell provides separate ports for read and write operations, including differential read bit lines. Prior to each read operation, the differential read bit lines are precharged to the low voltage level. During read operations, one of the two differential read bit lines is pulled high towards a high voltage level while the complementary bit line remains at the low voltage level resulting from the precharge. The difference in voltage between the differential read bit lines is sensed to determine the value stored in each 8-transistor SRAM storage cell and complete the read operation.